AD9609BCPZRL7-65 (Analog) PDF资料下载 Datasheet(11/32 页)

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参数资料

型号：	AD9609BCPZRL7-65
厂商：	Analog Devices Inc
文件页数：	11/32页
文件大小：	0K
描述：	IC ADC 10BIT SPI/SRL 65M 32LFCSP
标准包装：	1,500
位数：	10
采样率（每秒）：	65M
数据接口：	串行，SPI?
转换器数目：	1
功率耗散（最大）：	78mW
电压电源：	模拟和数字
工作温度：	-40°C ~ 85°C
安装类型：	表面贴装
封装/外壳：	32-VFQFN 裸露焊盘，CSP
供应商设备封装：	32-LFCSP-VQ
包装：	带卷 (TR)
输入数目和类型：	2 个单端，单极；1 个差分，单极

AD9609

Rev. 0 | Page 19 of 32

VOLTAGE REFERENCE

A stable and accurate 1.0 V voltage reference is built into the

AD9609. The VREF can be configured using either the internal

1.0 V reference or an externally applied 1.0 V reference voltage.

The various reference modes are summarized in the sections that

follow. The Reference Decoupling section describes the best

practices for PCB layout of VREF.

Internal Reference Connection

A comparator within the AD9609 detects the potential at the

SENSE pin and configures the reference into two possible

modes, which are summarized in Table 10. If SENSE is grounded,

the reference amplifier switch is connected to the internal resistor

divider (see Figure 42), setting VREF to 1.0 V.

VREF

SENSE

0.5V

ADC

SELECT

LOGIC

0.1F

1.0F

VIN–

VIN+

ADC

CORE

Figure 42. Internal Reference Configuration

In either internal or external reference mode, the maximum

input range of the ADC can be varied by configuring SPI

Address 0x18 as shown in Table 11, resulting in a selectable

differential span from 1 V p-p to 2 V p-p.

If the internal reference of the AD9609 is used to drive multiple

converters to improve gain matching, the loading of the reference

by the other converters must be considered. Figure 43 shows

how the internal reference voltage is affected by loading.

–3.0

LOAD CURRENT (mA)

NCE

(

)

–0.5

–1.0

–1.5

–2.0

–2.5

0.2

0.4

0.6

0.8

1.0

1.4

1.6

1.8

1.2

INTERNAL VREF = 0.996V

Figure 43. VREF Accuracy vs. Load Current

External Reference Operation

The use of an external reference may be necessary to enhance

the gain accuracy of the ADC or improve thermal drift charac-

teristics. Figure 44 shows the typical drift characteristics of the

internal reference in 1.0 V mode.

–1

–2

–3

–4

–5

–6

–40

–20

TEMPERATURE (°C)

RRO

(

)

VREF ERROR (mV)

-05

Figure 44. Typical VREF Drift

When the SENSE pin is tied to AVDD, the internal reference is

disabled, allowing the use of an external reference. An internal

reference buffer loads the external reference with an equivalent

7.5 kΩ load (see Figure 27). The internal buffer generates the posi-

tive and negative full-scale references for the ADC core. Therefore,

the external reference must be limited to a maximum of 1.0 V.

Table 10. Reference Configuration Summary

Selected Mode

SENSE Voltage (V)

Resulting VREF (V)

Resulting Differential Span (V p-p)

Fixed Internal Reference

AGND to 0.2

1.0 internal

2.0

Fixed External Reference

AVDD

1.0 applied to external VREF pin

2.0

Table 11. Scaled Differential Span Summary

Selected Mode

Resulting VREF (V)

SPI Register 0x18 (Hex)

Resulting Differential Span (V p-p)