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参数资料
| 型号： | AD9633BCPZRL7-80 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 18/40页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT SRL 80MSPS 48LFCSP |
| 标准包装： | 750 |
| 位数： | 12 |
| 采样率（每秒）： | 80M |
| 数据接口： | LVDS，串行，SPI? |
| 转换器数目： | 4 |
| 功率耗散（最大）： | 389mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 48-LFCSP-WQ（7x7） |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 4 个差分，双极 |
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Data Sheet
AD9633
Rev. 0 | Page 25 of 40
applications, drive the CLK+ pin directly from a CMOS gate, and
bypass the CLK pin to ground with a 0.1 μF capacitor (see
Input Clock Divider
The AD9633 contains an input clock divider with the ability
to divide the input clock by integer values between 1 and 8.
The AD9633 clock divider can be synchronized using the
external SYNC input. Bit 0 and Bit 1 of Register 0x109 allow the
clock divider to be resynchronized on every SYNC signal or
only on the first SYNC signal after the register is written. A
valid SYNC causes the clock divider to reset to its initial state.
This synchronization feature allows multiple parts to have their
clock dividers aligned to guarantee simultaneous input sampling.
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate a vari-
ety of internal timing signals and, as a result, may be sensitive to
clock duty cycle. Commonly, a ±5% tolerance is required on the
clock duty cycle to maintain dynamic performance characteristics.
The AD9633 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling (falling) edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows the user to
provide a wide range of clock input duty cycles without affecting
the performance of the AD9633. Noise and distortion perform-
ance are nearly flat for a wide range of duty cycles with the DCS
on, as shown in Figure 63.
73
55
40
60
S
NRF
S
(
d
B
F
S
)
DUTY CYCLE (%)
10
073
-06
9
63
61
57
59
65
67
71
69
42
44
46
48
50
52
54
56
58
SNRFS (DCS OFF)
SNRFS (DCS ON)
Figure 63. SNR vs. DCS On/Off
Jitter in the rising edge of the input is still of concern and is not
easily reduced by the internal stabilization circuit. The duty
cycle control loop does not function for clock rates less than
20 MHz, nominally. The loop has a time constant associated
with it that must be considered in applications in which the
clock rate can change dynamically. A wait time of 1.5 μs to 5 μs
is required after a dynamic clock frequency increase or decrease
before the DCS loop is relocked to the input signal.
100
0.1F
240
50k
CLK–
CLK+
CLOCK
INPUT
CLOCK
INPUT
ADC
AD951x
PECL DRIVER
100
73-
066
Figure 64. Differential PECL Sample Clock (Up to 1 GHz)
100
0.1F
50k
CLK–
CLK+
ADC
CLOCK
INPUT
CLOCK
INPUT
AD951x
LVDS DRIVER
100
73-
067
Figure 65. Differential LVDS Sample Clock (Up to 1 GHz)
OPTIONAL
100
0.1F
501
150 RESISTOR IS OPTIONAL.
CLK–
CLK+
ADC
VCC
1k
CLOCK
INPUT
AD951x
CMOS DRIVER
100
73-
0
68
Figure 66. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9634 | 制造商:AD 制造商全称:Analog Devices 功能描述:12-Bit, 170 MSPS/210 MSPS/250 MSPS |
| AD9634-170EBZ | 功能描述:数据转换 IC 开发工具 12 Bit 170 Msps ADC RoHS:否 制造商:Texas Instruments 产品:Demonstration Kits 类型:ADC 工具用于评估:ADS130E08 接口类型:SPI 工作电源电压:- 6 V to + 6 V |
| AD9634-210EBZ | 功能描述:数据转换 IC 开发工具 12 Bit 210 Msps ADC RoHS:否 制造商:Texas Instruments 产品:Demonstration Kits 类型:ADC 工具用于评估:ADS130E08 接口类型:SPI 工作电源电压:- 6 V to + 6 V |
| AD9634-250EBZ | 功能描述:数据转换 IC 开发工具 12 Bit 250 Msps ADC RoHS:否 制造商:Texas Instruments 产品:Demonstration Kits 类型:ADC 工具用于评估:ADS130E08 接口类型:SPI 工作电源电压:- 6 V to + 6 V |
| AD9634BCPZ-170 | 功能描述:IC ADC 12BIT 170MSPS 32-LFCSP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 其它有关文件:TSA1204 View All Specifications 标准包装:1 系列:- 位数:12 采样率（每秒）:20M 数据接口:并联 转换器数目:2 功率耗散（最大）:155mW 电压电源:模拟和数字 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-TQFP 供应商设备封装:48-TQFP（7x7） 包装:Digi-Reel® 输入数目和类型:4 个单端，单极；2 个差分，单极 产品目录页面:1156 (CN2011-ZH PDF) 其它名称:497-5435-6 |
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