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参数资料
| 型号： | AD9643BCPZ-210 |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | ADC |
| 英文描述： | 2-CH 14-BIT FLASH METHOD ADC, PARALLEL ACCESS, QCC64 |
| 封装： | 9 X 9 MM, ROHS COMPLIANT, MO-220VMMD-4, LFCSP-64 |
| 文件页数： | 26/36页 |
| 文件大小： | 1659K |
| 代理商： | AD9643BCPZ-210 |
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AD9643
Rev. A | Page 32 of 36
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 14 are not currently supported for this device.
Table 14. Memory Map Registers
Addr
(Hex)
Register
Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
(Hex)
Default
Notes/
Comments
Chip Configuration Registers
0x00
SPI port
configuration
0
LSB first
Soft reset
1
Soft reset
LSB first
0
0x18
The nibbles
are mirrored
so that LSB
first mode
or MSB first
mode
registers
correctly,
regardless
of shift
mode.
0x01
Chip ID
(global)
8-bit chip ID[7:0]
(AD9643 = 0x82)
(default)
0x82
Read only.
0x02
Chip grade
(global)
Open
Speed grade ID
00 = 250 MSPS
Open
Speed
grade ID
used to
differentiate
devices;
read only.
Channel Index and Transfer Registers
0x05
Channel index
(global)
Open
ADC B
(default)
ADC A
(default)
0x03
Bits are
set to
determine
which
device on
the chip
receives the
next write
command;
applies to
local
registers
only.
0xFF
Transfer
(global)
Open
Transfer
0x00
Synchro-
nously
transfers
data from
the master
shift register
to the slave.
ADC Functions
0x08
Power modes
(local)
Open
External
power-
down pin
function
(local)
0 = power-
down
1 = standby
Open
Internal power-down mode
(local)
00 = normal operation
01 = full power-down
10 = standby
11 = reserved
0x00
Determines
various
generic
modes of
chip
operation.
0x09
Global clock
(global)
Open
Duty cycle
stabilizer
(default)
0x01
0x0B
Clock divide
(global)
Open
Input clock divider phase adjust
000 = no delay
001 = 1 input clock cycle
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
111 = 7 input clock cycles
Clock divide ratio
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
0x00
Clock
divide
values
other than
000 auto-
matically
cause the
duty cycle
stabilizer to
become
active.
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