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| 型号： | AD9708-EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 12/16页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9708 |
| 产品培训模块： | DAC Architectures |
| 标准包装： | 1 |
| 系列： | TxDAC® |
| DAC 的数量： | 1 |
| 位数： | 8 |
| 采样率（每秒）： | 125M |
| 数据接口： | 并联 |
| 设置时间： | 35ns |
| DAC 型： | 电流 |
| 工作温度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD9708 |
| 相关产品： | AD9708ARZRL-ND - IC DAC 8BIT 100MSPS 28-SOIC AD9708ARZ-ND - IC DAC 8BIT 100MSPS 28-SOIC AD9708ARUZRL7-ND - IC DAC 8BIT 100MSPS 28-TSSOP TR AD9708ARUZ-ND - IC DAC 8BIT 100MSPS 28-TSSOP AD9708ARURL7-ND - IC DAC 8BIT 100MSPS 28-TSSOP AD9708ARU-ND - IC DAC 8BIT 100MSPS 28-TSSOP AD9708AR-ND - IC DAC 8BIT 100MSPS 28-SOIC |
AD9708
–5–
REV. B
DEFINITIONS OF SPECIFICATIONS
Linearity Error (Also Called Integral Nonlinearity or INL)
Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.
Differential Nonlinearity (or DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Monotonicity
A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.
Offset Error
The deviation of the output current from the ideal of zero is
called offset error. For IOUTA, 0 mA output is expected when
the inputs are all 0s. For IOUTB, 0 mA output is expected
when all inputs are set to 1s.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.
Output Compliance Range
The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown resulting in
nonlinear performance.
Temperature Drift
Temperature drift is specified as the maximum change from the
ambient (+25
°C) value to the value at either T
MIN or TMAX. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per degree C. For reference drift, the drift is
reported in ppm per degree C.
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.
Settling Time
The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.
Spurious-Free Dynamic Range
The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.
Signal-to-Noise and Distortion (S/N+D, SINAD) Ratio
S/N+D is the ratio of the rms value of the measured output
signal to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/N+D is expressed in decibels.
Total Harmonic Distortion
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured output signal. It is
expressed as a percentage or in decibels (dB).
DVDD
DCOM
RETIMED
CLOCK
OUTPUT*
DIGITAL
DATA
TEKTRONIX
AWG-2021
LECROY 9210
PULSE GENERATOR
CLOCK
OUTPUT
50
20pF
50
20pF
TO HP3589A
SPECTRUM/
NETWORK
ANALYZER
50
INPUT
* AWG2021 CLOCK RETIMED
SUCH THAT DIGITAL DATA
TRANSITIONS ON FALLING EDGE
OF 50% DUTY CYCLE CLOCK.
+1.20V REF
REFLO
REF IO
FS ADJ
50pF
COMP1
0.1 F
CURRENT
SOURCE
ARRAY
+5V
AVDD
SEGMENTED
SWITCHES
LATCHES
DVDD
DCOM
CLOCK
SLEEP
IOUTA
IOUTB
COMP2
ACOM
0.1 F
+5V
RSET
2k
0.1 F
AD9708
50
Figure 2. Basic AC Characterization Test Setup
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