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参数资料
| 型号： | AD9755-EB |
| 厂商： | Analog Devices Inc |
| 文件页数： | 4/28页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9755 |
| 产品培训模块： | DAC Architectures |
| 标准包装： | 1 |
| 系列： | TxDAC+® |
| DAC 的数量： | 1 |
| 位数： | 14 |
| 采样率（每秒）： | 300M |
| 数据接口： | 并联 |
| 设置时间： | 11ns |
| DAC 型： | 电流 |
| 工作温度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD9755 |
| 相关产品： | AD9755ASTZRL-ND - IC DAC 14BIT 300MSPS 48-LQFP AD9755ASTZ-ND - IC DAC 14BIT 300MSPS 48-LQFP |
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REV. B
AD9755
–12–
The effects of phase noise on the AD9755’s SNR performance
become more noticeable at higher reconstructed output frequen-
cies and signal levels. Figure 8 compares the phase noise of a
full-scale sine wave at exactly fDATA/4 at different data rates
(thus carrier frequency) with the optimum DIV1, DIV0 setting.
FREQUENCY OFFSET (MHz)
0
–20
–110
5
1
0
NOISE
DENSITY
(dBm/Hz)
–10
–30
–40
–50
–60
–70
–80
–90
–100
234
PLL ON, fDATA = 150MSPS
PLL OFF, fDATA = 50MSPS
Figure 8. Phase Noise of PLL Clock Multiplier at
fOUT = fDATA/4 at Different fDATA Settings with DIV0/DIV1
Optimized, Using R&S FSEA30 Spectrum Analyzer
SNR is partly a function of the jitter generated by the clock
circuitry. As a result, any noise on PLLVDD or CLKVDD may
decrease the SNR at the output of the DAC. To minimize this
potential problem, PLLVDD and CLKVDD can be connected
to DVDD using an LC filter network similar to the one shown
in Figure 9.
100 F
ELECT.
10 F–22 F
TANT.
0.1 F
CER.
TTL/CMOS
LOGIC
CIRCUITS
3.3V POWER SUPPLY
FERRITE
BEADS
CLKVDD
PLLVDD
CLKCOM
Figure 9. LC Network for Power Filtering
DAC TIMING WITH PLL ACTIVE
As described in Figure 7, in PLL ACTIVE mode, Port 1 and
Port 2 input latches are updated on the rising edge of CLK. On
the same rising edge, data previously present in the input Port 2
latch is written to the DAC output latch. The DAC output will
update after a short propagation delay (tPD).
Following the rising edge of CLK, at a time equal to half of its
period, the data in the Port 1 latch will be written to the DAC
output latch, again with a corresponding change in the DAC
output. Due to the internal PLL, the time at which the data in
the Port 1 and Port 2 input latches is written to the DAC latch
is independent of the duty cycle of CLK.
When using the PLL,
the external clock can be operated at any duty cycle that
meets the specified input pulsewidth.
On the next rising edge of CLK, the cycle begins again with the
two input port latches being updated and the DAC output latch
being updated with the current data in the Port 2 input latch.
PLL DISABLED MODE
When PLLVDD is grounded, the PLL is disabled. An external
clock must now drive the CLK inputs at the desired DAC output
update rate. The speed and timing of the data present at input
Ports 1 and 2 are now dependent on whether or not the AD9755
is interleaving the digital input data, or only responding to data
on a single port. Figure 10 is a functional block diagram of the
AD9755 clock control circuitry with the PLL disabled.
PLLVDD
TO DAC
LATCH
PLLLOCK
CLOCK
LOGIC
( 1 OR
2)
DIFFERENTIAL-
TO-
SINGLE-ENDED
AMP
TO
INTERNAL
MUX
CLKIN+
CLKIN–
AD9755
RESET DIV0 DIV1
TO INPUT
LATCHES
Figure 10. Clock Circuitry with PLL Disabled
DIV0 and DIV1 no longer control the PLL, but are used to set
the control on the input mux for either interleaving or non-
interleaving the input data. The different modes for states of
DIV0 and DIV1 are given in Table II.
Table II. Input Mode for DIV0,
DIV1 Levels with PLL Disabled
Input Mode
DIV1
DIV0
Interleaved (2
×)0
0
Noninterleaved
Port 1 Selected
0
1
Port 2 Selected
1
0
Not Allowed
1
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| AD9760AR | 功能描述:IC DAC 10BIT 125MSPS 28-SOIC RoHS:否 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:TxDAC® 标准包装:47 系列:- 设置时间:2µs 位数:14 数据接口:并联 转换器数目:1 电压电源:单电源 功率耗散（最大）:55µW 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:管件 输出数目和类型:1 电流，单极；1 电流，双极 采样率（每秒）:* |
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