参数资料
型号: AD9760ARZ50RL
厂商: Analog Devices Inc
文件页数: 7/23页
文件大小: 0K
描述: IC DAC 10BIT 125MSPS 28TSSOP
标准包装: 1,000
系列: TxDAC®
设置时间: 35ns
位数: 10
转换器数目: 1
电压电源: 模拟和数字
功率耗散(最大): 175mW
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-SOIC(0.295",7.50mm 宽)
供应商设备封装: 28-SOIC
包装: 带卷 (TR)
输出数目和类型: 2 电流,单极;2 电流,双极
采样率(每秒): 60M
AD9760
–15–
REV. B
Note, the clock input could also be driven via a sine wave that is
centered around the digital threshold (i.e., DVDD/2), and
meets the min/max logic threshold. This will typically result in a
slight degradation in the phase noise, that becomes more notice-
able at higher sampling rates and output frequencies. Also, at
higher sampling rates, the 20% tolerance of the digital logic
threshold should be considered since it will affect the effective
clock duty cycle and subsequently cut into the required data
setup and hold times.
SLEEP MODE OPERATION
The AD9760 has a power-down function that turns off the out-
put current and reduces the supply current to less than 8.5 mA
over the specified supply range of 2.7 V to 5.5 V and tempera-
ture range. This mode can be activated by applying a logic level
“1” to the SLEEP pin. This digital input also contains an active
pull-down circuit that ensures that the AD9760 remains enabled
if this input is left disconnected. The SLEEP input with active
pull-down requires <40
A of drive current.
The power-up and power-down characteristics of the AD9760
are dependent upon the value of the compensation capacitor
connected to COMP1. With a nominal value of 0.1
F, the
AD9760 takes less than 5
s to power down and approximately
3.25 ms to power back up. Note, the SLEEP MODE should not
be used when the external control amplifier is used as shown in
Figure 45.
POWER DISSIPATION
The power dissipation, PD, of the AD9760 is dependent on
several factors that include: (1) AVDD and DVDD, the power
supply voltages; (2) IOUTFS, the full-scale current output; (3)
fCLOCK, the update rate; (4) and the reconstructed digital input
waveform. The power dissipation is directly proportional to the
analog supply current, IAVDD, and the digital supply current,
IDVDD. IAVDD is directly proportional to IOUTFS as shown in Fig-
ure 47 and is insensitive to fCLOCK.
IOUTFS – mA
30
0
220
4
6
8
10
12
141618
25
20
15
10
5
I AVDD
mA
Figure 47. IAVDD vs. IOUTFS
Conversely, IDVDD is dependent on both the digital input wave-
form, fCLOCK, and digital supply DVDD. Figures 48 and 49
show IDVDD as a function of full-scale sine wave output ratios
(fOUT/fCLOCK) for various update rates with DVDD = 5 V and
DVDD = 3 V, respectively. Note how IDVDD is reduced by more
than a factor of 2 when DVDD is reduced from 5 V to 3 V.
RATIO (fOUT/fCLK)
18
16
0
0.01
1
0.1
I DVDD
mA
8
6
4
2
12
10
14
5MSPS
25MSPS
50MSPS
100MSPS
125MSPS
Figure 48. IDVDD vs. Ratio @ DVDD = 5 V
RATIO (fOUT/fCLK)
8
0
0.01
1
0.1
I DVDD
mA
6
4
2
5MSPS
25MSPS
50MSPS
100MSPS
125MSPS
Figure 49. IDVDD vs. Ratio @ DVDD = 3 V
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