参数资料
| 型号： | AD9776BSVZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 32/56页 |
| 文件大小： | 0K |
| 描述： | IC DAC 12BIT DUAL 1GSPS 100TQFP |
| 产品培训模块： | DAC Architectures |
| 标准包装： | 1,000 |
| 位数： | 12 |
| 数据接口： | 并联 |
| 转换器数目： | 2 |
| 电压电源： | 模拟和数字 |
| 功率耗散（最大）： | 300mW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-TQFP 裸露焊盘 |
| 供应商设备封装： | 100-TQFP-EP（14x14） |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 4 电流，单极 |
| 采样率（每秒）： | 1G |
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AD9776/AD9778/AD9779
Rev. A | Page 38 of 56
(Register 0x09, Bits<2:0>) should be set to 111. The PLL control
voltage (Register 0x0A, Bits<7:5>) is read back and is propor-
tional to the dc voltage at the internal loop filter output. With
the PLL bias settings given in this section, the readback from
the PLL control voltage should typically be 010, or possibly 001
or 011. Anything outside of this range indicates that the PLL is
not operating correctly.
0
4
8
12
16
20
24
28
32
36
40
44
48
52
56
60
850
2150
2050
1950
1850
1750
1650
1450
1550
1350
1250
1150
1050
950
FVCO (MHz)
P
LL
BAND
05361-072
Figure 75. Typical PLL Band Select vs. Frequency at 25°C
0
4
8
12
16
20
24
28
32
36
40
44
48
52
56
60
850
2150
2050
1950
1850
1750
1650
1450
1550
1350
1250
1150
1050
950
FVCO (MHz)
P
LL
BAND
05361-113
Figure 76. Typical PLL Band Select vs. Frequency over Temperature
The AD977x has an autosearch feature that determines the
optimal settings for the PLL. To enable the autosearch mode, set
Register 0x08, Bits<7:2> to 11111b, and read back the value
from Register 0x08, Bits<7:2>. Autosearch mode is intended to
find the optimal PLL settings only, after which the same settings
should be applied in manual mode. It is not recommended that
the PLL be set to autosearch mode during regular operation.
FULL-SCALE CURRENT GENERATION
Internal Reference
Full-scale current on the I DAC and Q DAC can be set from
8.66 mA to 31.66 mA. Initially, the 1.2 V band gap reference is
used to set up a current in an external resistor connected to
I120 (Pin 75). A simplified block diagram of the reference
circuitry is shown in Figure 77. The recommended value for the
external resistor is 10 kΩ, which sets up an IREFERENCE in the
resistor of 120 μA, which in turn provides a DAC output full-
scale current of 20 mA. Because the gain error is a linear
function of this resistor, a high precision resistor improves gain
matching to the internal matching specification of the devices.
Internal current mirrors provide a current-gain scaling, where
I DAC or Q DAC gain is a 10-bit word in the SPI port register
(Register 0x0A, Register 0x0B, Register 0x0E, and Register 0x0F).
The default value for the DAC gain registers gives an IFS of
approximately 20 mA, where IFS is equal to
32
1024
6
12
27
V
2
.
1
×
×
+
×
gain
DAC
R
I DAC
DAC FULL-SCALE
REFERENCE
CURRENT
SCALING
I DAC GAIN
Q DAC GAIN
Q DAC
AD9779
VREF
10k
Ω
1.2V BAND GAP
0.1
μF
I120
05361-073
Figure 77. Reference Circuitry
35
0
1000
DAC GAIN CODE
I FS
(m
A
)
30
25
20
15
10
5
200
400
600
800
05
36
1-
07
4
Figure 78. IFS vs. DAC Gain Code
Application of Auxiliary DACs in Single Sideband
Transmitter
Two auxiliary DACs are provided on the AD977x. The full-scale
output current on these DACs is derived from the 1.2 V band
gap reference and external resistor. The gain scale from the ref-
erence amplifier current IREFERENCE to the auxiliary DAC reference
current is 16.67 with the auxiliary DAC gain set to full scale
(10-bit values, SPI Register 0x0D and SPI Register 0x11), this
gives a full-scale current of approximately 2 mA for auxiliary
DAC1 and auxiliary DAC2. The auxiliary DAC outputs are not
differential. Only one side of the auxiliary DAC (P or N) is
active at one time. The inactive side goes into a high impedance
state (>100 kΩ). In addition, the P or N outputs can act as
current sources or sinks. The control of the P and N side for
both auxiliary DACs is via Register 0x0E and Register 0x10,
Bits<7:6>. When sourcing current, the output compliance
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