参数资料
| 型号： | AD9786BSVZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 39/56页 |
| 文件大小： | 0K |
| 描述： | IC DAC 16BIT INTERPOL/SP 80TQFP |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 标准包装： | 1,000 |
| 系列： | TxDAC+® |
| 位数： | 16 |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 电压电源： | 单电源 |
| 功率耗散（最大）： | 1.25W |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 80-TQFP 裸露焊盘 |
| 供应商设备封装： | 80-TQFP-EP（12x12） |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 2 电流，单极 |
| 采样率（每秒）： | 500M |
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AD9786
Rev. B | Page 44 of 56
OPERATING THE AD9786 REV. F EVALUATION BOARD
This section provides information to power up the board and
verify correct operation; a description of more advanced modes
of operation has been omitted.
POWER SUPPLIES
The AD9786 Rev. F evaluation board has five power supply
connectors, labeled AVDD1, AVDD2, ACVDD/ADVDD,
CLKVDD, and DVDD, whereas the AD9786 has seven power
supply domains. To reconcile the power supply domains on the
chip with the power supply connectors on the evaluation board,
use Table 38.
Additionally, the DRVDD power supply on the AD9786 is used
to supply power for the digital input bus. DRVDD should be
run from 3.3 V. On the evaluation board, DRVDD is jumper-
selectable by JP1, which is just to the left of the chip on the
evaluation board. With the jumper set to the 3.3 V position, the
DRVDD chip receives its power from VDD3IN.
PECL CLOCK DRIVER
The AD9786 system clock is driven from an external source via
Connector S1. The AD9786 evaluation board includes an
ON Semiconductor MC100EPT22 PECL clock driver. In the
factory, the evaluation board is set to use this PECL driver as a
single-ended-to-differential clock receiver. The PECL driver can
be set to run from 2.5 V from the CLKVDD power connector
or 3.3 V from the VDD3IN power connector. This setting is
done via Jumper JP2, situated next to the CLKVDD power
connector, and by setting Input Bias Resistor R23 and Input
Bias Resistor R4 on the evaluation board. The factory default is
for the PECL driver to be powered from CLKVDD at 2.5 V
(R23 = 90.9 Ω, R4 = 115 Ω). To operate the PECL driver with
a 3.3 V supply, R23 must be replaced with a 115 Ω resistor; R4
must be replaced with a 90.9 Ω resistor; and the position of JP2
must be changed. The schematic of the PECL driver section of
the evaluation board is shown in Figure 85. A low jitter sine
wave should be used as the clock source. Care must be taken to
ensure that the clock amplitude does not exceed the power
supply rails for the PECL driver.
03152-085
U2
7
1
2
COND;5
CLKVDDS;8
C32
0.1
μF
R23
115
Ω
R4
90.9
Ω
ACLKX
CLKVDDS
R5
50
Ω
R7
50
Ω
R6
50
Ω
CLKVDDS
MC100EPT22
CLK+
CLK–
Figure 85. PECL Driver on AD9786 Rev. F Evaluation Board
Table 38. Power Supply Domains on AD9786 Rev. F Evaluation Board
Evaluation Board Label/PS Domain on Chip
Nominal Power
Supply Voltage (V)
Description
DVDD
2.5
SPI port
CLKVDD
2.5
Clock circuitry
ACVDD/ADVDD
2.5
Analog circuitry containing clock and digital interface circuitry
AVDD2
3.3
Switching analog circuitry
AVDD1
3.3
Analog output circuitry
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相关代理商/技术参数 |
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| AD9786-EB | 制造商:Rochester Electronics LLC 功能描述:EVAL BOARD FOR AD9786 - Bulk |
| AD9786-EBZ | 功能描述:BOARD EVALUATION FOR AD9786 RoHS:是 类别:编程器，开发系统 >> 评估板 - 数模转换器 (DAC) 系列:TxDAC+® 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- DAC 的数量:4 位数:12 采样率（每秒）:- 数据接口:串行，SPI? 设置时间:3µs DAC 型:电流/电压 工作温度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9786XSV | 制造商:Analog Devices 功能描述:- Bulk |
| AD9787 | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual 12-/14-/16-Bit 800 MSPS DAC with Low Power 32-Bit Complex NCO |
| AD9787BSVZ | 功能描述:IC DAC 14BIT 800MSPS 100TQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:TxDAC® 标准包装:1 系列:- 设置时间:4.5µs 位数:12 数据接口:串行，SPI? 转换器数目:1 电压电源:单电源 功率耗散（最大）:- 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOICN 包装:剪切带 (CT) 输出数目和类型:1 电压，单极；1 电压，双极 采样率（每秒）:* 其它名称:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
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