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| 型号： | AD9832BRUZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/28页 |
| 文件大小： | 0K |
| 描述： | IC DDS 10BIT 25MHZ CMOS 16TSSOP |
| 产品培训模块： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 标准包装： | 1,000 |
| 分辨率（位）： | 10 b |
| 主 fclk： | 25MHz |
| 调节字宽（位）： | 32 b |
| 电源电压： | 2.97 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-TSSOP |
| 包装： | 带卷 (TR) |
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AD9832
Data Sheet
Rev. E | Page 16 of 28
Table 11. Writing to the AD9832 Data Registers
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
C3
C2
C1
C0
A3
A2
A1
A0
MSB
LSB
1
X = don’t care.
Table 12. Setting SYNC and SELSRC
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
0
SYNC
SELSRC
1
X = don’t care.
Table 13. Power-Down, Resetting and Clearing the AD9832
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
SLEEP
RESET
CLR
1
X = don’t care.
LATENCY
Associated with each operation is a latency. When inputs
FSELECT/PSEL change value, there is a pipeline delay before
control is transferred to the selected register; there is a pipeline
delay before the analog output is controlled by the selected
register. When times t11 and t11A are met, PSEL0, PSEL1, and
FSELECT have latencies of six MCLK cycles when SYNC = 0.
When SYNC = 1, the latency is increased to 8 MCLK cycles.
When times t11 and t11A are not met, the latency can increase by
one MCLK cycle. Similarly, there is a latency associated with
each write operation. If a selected frequency/phase register is
loaded with a new word, there is a delay of 6 to 7 MCLK cycles
before the analog output will change (there is an uncertainty of
one MCLK cycle regarding the MCLK rising edge at which the
data is loaded into the destination register). When SYNC = 1,
the latency is 8 or 9 MCLK cycles.
FLOWCHARTS
The flowchart in Figure 24 shows the operating routine for the
AD9832. When the AD9832 is powered up, the part should be
reset, which resets the phase accumulator to zero so that the
analog output is at full scale. To avoid spurious DAC outputs
while the AD9832 is being initialized, the RESET bit should be
set to 1 until the part is ready to begin generating an output.
Taking CLR high sets SYNC and SELSRC to 0 so that the
FSELECT/PSELx pins are used to select the frequency/phase
registers, and the synchronization circuitry is bypassed. A write
operation is needed to the SYNC/SELSRC register to enable the
synchronization circuitry or to change control to the FSELECT/
PSEL bits. RESET does not reset the phase and frequency registers.
These registers will contain invalid data and, therefore, should
be set to a known value by the user. The RESET bit is then set to 0
to begin generating an output. A signal will appear at the DAC
output 6 MCLK cycles after RESET is set to 0.
The analog output is fMCLK/232 × FREG, where FREG is the value
loaded into the selected frequency register. This signal is phase
shifted by the amount specified in the selected phase register
(2π/4096 × PHASEx REG, where PHASEx REG is the value
contained in the selected phase register).
Control of the frequency/phase registers can be interchanged
from the pins to the bits.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9833 | 制造商:AD 制造商全称:Analog Devices 功能描述:+2.5 V to +5.5 V, 25 MHz Low Power CMOS Complete DDS |
| AD9833BRM | 功能描述:IC WAVEFORM GEN PROG 10-MSOP RoHS:否 类别:集成电路 (IC) >> 接口 - 直接数字合成 (DDS) 系列:- 产品变化通告:Product Discontinuance 27/Oct/2011 标准包装:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 调节字宽（位）:32 b 电源电压:2.97 V ~ 5.5 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:带卷 (TR) |
| AD9833BRM-REEL | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 25MHz 1-DAC 10-Bit Serial 10-Pin MSOP T/R 制造商:Analog Devices 功能描述:PROGRAMMABLE WAVEFORM GENERATOR 10MSOP - Tape and Reel |
| AD9833BRM-REEL7 | 功能描述:IC WAVEFORM GEN PROG 10-MSOP RoHS:否 类别:集成电路 (IC) >> 接口 - 直接数字合成 (DDS) 系列:- 产品变化通告:Product Discontinuance 27/Oct/2011 标准包装:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 调节字宽（位）:32 b 电源电压:2.97 V ~ 5.5 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:带卷 (TR) |
| AD9833BRMZ | 功能描述:IC WAVEFORM GENERTR PROG 10-MSOP RoHS:是 类别:集成电路 (IC) >> 接口 - 直接数字合成 (DDS) 系列:- 产品变化通告:Product Discontinuance 27/Oct/2011 标准包装:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 调节字宽（位）:32 b 电源电压:2.97 V ~ 5.5 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:带卷 (TR) |
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