参数资料
型号: AD9834BRU-REEL
厂商: Analog Devices Inc
文件页数: 11/32页
文件大小: 0K
描述: IC DDS 10BIT 50MHZ LP 20-TSSOP
产品培训模块: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
设计资源: Amplitude Control Circuit for AD9834 Waveform Generator (CN0156)
标准包装: 2,500
分辨率(位): 10 b
主 fclk: 50MHz
调节字宽(位): 28 b
电源电压: 2.3 V ~ 5.5 V
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 20-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 20-TSSOP
包装: 带卷 (TR)
Data Sheet
AD9834
MUX
SLEEP12
SLEEP1
OPBITEN
IOUTB
IOUT
COMPARATOR
VIN
SIGN/PIB
MUX
MSB
SIGN BIT OUT
0
1
MUX
1
0
1
DIGITAL
OUTPUT
(ENABLE)
(LOW POWER)
10-BIT DAC
DIVIDE
BY 2
SIN
ROM
MODE + OPBITEN
PHASE
ACCUMULATOR
(28-BIT)
02705-
026
Figure 29. Function of Control Bits
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
B28
HLB
FSEL
PSEL
PIN/SW
RESET
SLEEP1
SLEEP12
OPBITEN
SIGN/PIB
DIV2
0
MODE
0
Table 6. Description of Bits in the Control Register
Bit
Name
Description
DB13
B28
Two write operations are required to load a complete word into either of the frequency registers.
B28 = 1 allows a complete word to be loaded into a frequency register in two consecutive writes. The first write
contains the 14 LSBs of the frequency word and the next write contains the 14 MSBs. The first two bits of each 16-bit
word define the frequency register the word is loaded to and should, therefore, be the same for both of the consecutive
writes. Refer to Table 10 for the appropriate addresses. The write to the frequency register occurs after both words have
been loaded. An example of a complete 28-bit write is shown in Table 11. Note however, that consecutive 28-bit writes
to the same frequency register are not allowed, switch between frequency registers to do this type of function.
B28 = 0, the 28-bit frequency register operates as two 14-bit registers, one containing the 14 MSBs and the other
containing the 14 LSBs. This means that the 14 MSBs of the frequency word can be altered independent of the 14 LSBs,
and vice versa. To alter the 14 MSBs or the 14 LSBs, a single write is made to the appropriate frequency address. The
Control Bit DB12 (HLB) informs the AD9834 whether the bits to be altered are the 14 MSBs or 14 LSBs.
DB12
HLB
This control bit allows the user to continuously load the MSBs or LSBs of a frequency register ignoring the remaining
14 bits. This is useful if the complete 28-bit resolution is not required. HLB is used in conjunction with DB13 (B28). This
control bit indicates whether the 14 bits being loaded are being transferred to the 14 MSBs or 14 LSBs of the addressed
frequency register. DB13 (B28) must be set to 0 to be able to change the MSBs and LSBs of a frequency word separately.
When DB13 (B28) = 1, this control bit is ignored.
HLB = 1 allows a write to the 14 MSBs of the addressed frequency register.
HLB = 0 allows a write to the 14 LSBs of the addressed frequency register.
DB11
FSEL
The FSEL bit defines whether the FREQ0 register or the FREQ1 register is used in the phase accumulator. See Table 8 to
select a frequency register.
DB10
PSEL
The PSEL bit defines whether the PHASE0 register data or the PHASE1 register data is added to the output of the phase
accumulator. See Table 9 to select a phase register.
DB9
PIN/SW
Functions that select frequency and phase registers, reset internal registers, and power down the DAC can be
implemented using either software or hardware. PIN/SW selects the source of control for these functions.
PIN/SW = 1 implies that the functions are being controlled using the appropriate control pins.
PIN/SW = 0 implies that the functions are being controlled using the appropriate control bits.
DB8
RESET
RESET = 1 resets internal registers to 0, this corresponds to an analog output of midscale.
RESET = 0 disables RESET. This function is explained in the RESET Function section.
DB7
SLEEP1
SLEEP1 = 1, the internal MCLK is disabled. The DAC output remains at its present value as the NCO is no longer
accumulating.
SLEEP1 = 0, MCLK is enabled. This function is explained in the SLEEP Function section.
DB6
SLEEP12
SLEEP12 = 1 powers down the on-chip DAC. This is useful when the AD9834 is used to output the MSB of the DAC data.
SLEEP12 = 0 implies that the DAC is active. This function is explained in the SLEEP Function section.
Rev. D | Page 19 of 32
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