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| 型号： | AD9837ACPZ-RL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 25/28页 |
| 文件大小： | 0K |
| 描述： | IC WAVEFORM GEN PROG 10LFCSP |
| 产品培训模块： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 标准包装： | 1 |
| 分辨率（位）： | 10 b |
| 主 fclk： | 5MHz |
| 调节字宽（位）： | 28 b |
| 电源电压： | 2.3 V ~ 5.5 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-WFDFN 裸露焊盘，CSP |
| 供应商设备封装： | 10-LFCSP-WD（3x3） |
| 包装： | 标准包装 |
| 其它名称： | AD9837ACPZ-RL7DKR |
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AD9837
Data Sheet
Rev. A | Page 6 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
COMP
1
VDD
2
CAP/2.5V
3
DGND
4
MCLK
5
VOUT
10
AGND
9
FSYNC
8
SCLK
7
SDATA
6
AD9837
TOP VIEW
(Not to Scale)
09070-
005
NOTES
1. CONNECT EXPOSED PAD
TO GROUND.
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
COMP
DAC Bias Pin. This pin is used for decoupling the DAC bias voltage.
2
VDD
Positive Power Supply for the Analog and Digital Interface Sections. The on-board 2.5 V regulator is also
supplied from VDD. VDD can have a value from 2.3 V to 5.5 V. A 0.1 F and a 10 F decoupling capacitor should
be connected between VDD and AGND.
3
CAP/2.5V
The digital circuitry operates from a 2.5 V power supply. This 2.5 V is generated from VDD using an on-board
regulator when VDD exceeds 2.7 V. The regulator requires a decoupling capacitor of 100 nF typical, which is
connected from CAP/2.5V to DGND. If VDD is less than or equal to 2.7 V, CAP/2.5V should be tied directly to
VDD to bypass the on-board regulator.
4
DGND
Digital Ground.
5
MCLK
Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK. The
output frequency accuracy and phase noise are determined by this clock.
6
SDATA
Serial Data Input. The 16-bit serial data-word is applied to this input.
7
SCLK
Serial Clock Input. Data is clocked into the AD9837 on each falling edge of SCLK.
8
FSYNC
Active Low Control Input. FSYNC is the frame synchronization signal for the input data. When FSYNC is taken
low, the internal logic is informed that a new word is being loaded into the device.
9
AGND
Analog Ground.
10
VOUT
Voltage Output. The analog and digital output from the AD9837 is available at this pin. An external load
resistor is not required because the device has a 200 resistor on board.
EP
Exposed Pad. Connect the exposed pad to ground.
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