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参数资料
| 型号： | AD9889BBSTZ-80 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 11/12页 |
| 文件大小： | 0K |
| 描述： | IC TRANSMITTER HDMI/DVI 80LQFP |
| 标准包装： | 90 |
| 类型： | HDMI，DVI 发射器 |
| 应用： | 录音机，机顶盒 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 80-LQFP |
| 供应商设备封装： | 80-LQFP（14x14） |
| 包装： | 托盘 |
| 配用： | AD9889B/PCBZ-ND - KIT EVALUATION FOR AD9889B |
AD9889B
Rev. A | Page 8 of 12
Pin No.
Mnemonic
Description
BGA
LFCSP
LQFP
K7, K8
27, 28
34, 35
Tx1/Tx1+
O
Differential Output Channel 1. Differential output of the
green data at 10× the pixel clock rate; supports TMDS logic level.
K4, K5
24, 25
30, 31
Tx0/Tx0+
O
Differential Output Channel 0. Differential output of the blue
data at 10× the pixel clock rate; TMDS logic level.
H10
32
40
INT
O
Interrupt. Open drain. A 2 kΩ pull-up resistor to the
microcontroller I/O supply is recommended.
J2, J5, J8, K9
19, 23, 29
24, 29, 36, 41
AVDD
P
1.8 V Power Supply for TMDS Outputs.
D5, D6, D7, E7
1, 48, 49
1, 61, 62, 63, 64
DVDD
P
1.8 V Power Supply for Digital and I/O Power Supply. These
pins supply power to the digital logic and I/Os. They should
be filtered and as quiet as possible.
G4, G5, J1
15, 16, 17,
16, 19, 20, 21
PVDD
P
1.8 V PLL Power Supply. The most sensitive portion of the
AD9889B is the clock generation circuitry. These pins provide
power to the clock PLL. The designer should provide quiet,
noise-free power to these pins.
D4, E4, F4, J4,
G6, J6, K6, F7,
G7, H9, J9
N/A
15, 17, 18, 22,
26, 32, 39, 42,
43, 59, 60, 79, 80
GND
P
Ground. The ground return for all circuitry on-chip. For best
practice, assemble the AD9889B on a single, solid ground
plane with careful attention given to ground current paths.
N/A
64, paddle
on bottom
side
N/A
DGND
P
Digital Ground. The ground return for all circuitry on-chip.
For best practice, assemble the AD9889B on a single, solid
ground plane with careful attention given to ground
current paths.
F9
36
47
SDA
C3
Serial Port Data I/O. This pin serves as the serial port data I/O
slave for register access. Supports CMOS logic levels from
1.8 V to 3.3 V.
F10
35
46
SCL
Serial Port Data Clock. This pin serves as the serial port data
clock slave for register access. Supports CMOS logic levels
from 1.8 V to 3.3 V.
E10
37
48
MDA
Serial Port Data I/O Master to HDCP Key EEPROM. Supports
CMOS logic levels from 1.8 V to 3.3 V.
E9
38
49
MCL
Serial Port Data Clock Master to HDCP Key EEPROM. Supports
CMOS logic levels from 1.8 V to 3.3 V.
G9
34
45
DDCSDA
Serial Port Data I/O to Receiver. This pin serves as the master
to the DDC bus. Supports a 5 V CMOS logic level.
G10
33
44
DDCSCL
Serial Port Data Clock to Receiver. This pin serves as the
master clock for the DDC bus. Supports a 5 V CMOS logic level.
1 I = input, O = output, P = power supply, C = control.
2 Pin J7 (BGA), Pin 26 (LFCSP), and Pin 33 (LQFP) are dual function pins: I2C selection and power-down control. The I2C selection function occurs at power-up; the power-
down control function occurs whenever the state of the pin is changed from its original state at power-up.
3 For a full description of the 2-wire serial interface and its functionality, obtain documentation by contacting NDA from ATV_VideoTx_Apps@analog.com.
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相关代理商/技术参数 |
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|---|---|
| AD9889B-KCPV-165 | 制造商:Analog Devices 功能描述:HIGH PERFORMANCE HDMI-/DVI TRANSMITTER - Bulk |
| AD9889BXBCZ-80 | 制造商:Analog Devices 功能描述:165 MHZ HIGH PERFORMANCE HDMI-/DVI TRANSMITTER - Bulk |
| AD9889BXCPZ-165 | 制造商:Analog Devices 功能描述:HIGH PERFORMANCE HDMI-/DVI TRANSMITTER - Bulk |
| ad9889kstz-80 | 制造商:Analog Devices 功能描述:HI-PERF HDMI/DVI TRANSMITTER 80LQFP - Trays 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD9889PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:High Performance HDMI/DVI Transmitter |
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