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| 型号： | AD9953YSVZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/32页 |
| 文件大小： | 0K |
| 描述： | IC DDS DAC 14BIT 1.8V 48TQFP |
| 产品培训模块： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 标准包装： | 500 |
| 分辨率（位）： | 14 b |
| 主 fclk： | 400MHz |
| 调节字宽（位）： | 32 b |
| 电源电压： | 1.71 V ~ 1.96 V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-TQFP 裸露焊盘 |
| 供应商设备封装： | 48-TQFP 裸露焊盘（7x7） |
| 包装： | 带卷 (TR) |
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AD9953
Rev. A | Page 20 of 32
address generator
the generator stops incrementing as the
te
e phase accumulator remains
al as
l
control bits of RSCW0 to Logic 010(b). In bidirectional
>
r
segment address ramp rate bits. The RAM
e beginning address, and the ramp rate timer
g-
te
e I/O
t.
enera-
r
in
f the
mp
as
rol the RAM in the
ies.
for continuous bidirectional ramp
the RAM address generator loads the RAM
ts of the current RSCW and the
its.
the ramp
te timer begins to count down to 1. When the ramp rate timer
ompletes a cycle, the RAM address generator increments to the
If the no-dwell bit is clear when the RAM
equals the final address,
terminal frequency has been reached. The sweep is comple
and does not restart until an I/O UPDATE or change in profile
is detected to enable another sweep from the beginning to the
final RAM address as described above.
If the no-dwell bit is set when the RAM address generator
equals the final address, after the next ramp rate timer cycle the
phase accumulator is cleared. Th
cleared until another sweep is initiated via an I/O UPDATE
input or change in profile.
Another application for ramp-up mode is nonsymmetrical FSK
modulation. With the RAM configured for two segments, using
the Profile<0> bit as the data input allows nonsymmetrical
ramped FSK.
Bidirectional Ramp Mode
Bidirectional ramp mode allows the AD9953 to offer a symme-
trical sweep between two frequencies using the Profile<0> sign
the control input. The AD9953 is programmed for bidirectiona
ramp mode by writing the RAM enable bit true and the RAM
mode
ramp mode, the Profile<1> input is ignored and the Profile<0
input is the ramp direction indicator. In this mode, the memory
is not segmented and uses only a single beginning and final
address. The address registers that affect the control of the RAM
are located in the RSCW associated with Profile 0.
Upon entering this mode (via an I/O UPDATE or changing
Profile<0>), the RAM address generator loads the RAM seg-
ment beginning address bits of RSCW0 and the ramp rate time
loads the RAM
drives data from th
begins to count down to 1. While operating in this mode, to
gling the Profile<0> pin does not cause the device to genera
an internal I/O UPDATE. When the Profile<0> pin is acting as
the ramp direction indicator, any transfer of data from th
buffers to the internal registers can only be initiated by a rising
edge on the I/O UPDATE pin.
RAM address control now is a function of the Profile<0> inpu
When the Profile<0> bit is a Logic 1, the RAM address g
tor increments to the next address when the ramp rate time
completes a cycle (and reloads to start the timer again). As
the ramp-up mode, this sequence continues until the RAM
address generator has incremented to an address equal to the
final address as long as the Profile<0> input remains high. I
Profile<0> input goes low, the RAM address generator imme-
diately decrements and the ramp rate timer is reloaded. The
RAM address generator will continue to decrement at the ra
rate period until the RAM address is equal to the beginning
address as long as the Profile<0> input remains low.
The sequence of ramping up and down is controlled via the
Profile<0> input signal for as long as the part is programmed
into this mode. The no-dwell bit is a Don’t Care in this mode
is all data in the RAM segment control words associated with
Profiles 1, 2, and 3. Only the information in the RAM segment
control word for Profile 0 is used to cont
bidirectional ramp mode.
Continuous Bidirectional Ramp Mode
Continuous bidirectional ramp mode allows the AD9953 to
offer an automatic symmetrical sweep between two frequenc
The AD9953 is programmed
mode by writing the RAM enable bit true and the RAM mode
control bits of each profile to be used to Logic 011(b).
Upon entering this mode (via an I/O UPDATE or changing
Profile<1:0>),
segment beginning address bi
ramp rate timer loads the RAM segment address ramp rate bits.
The RAM drives data from the beginning address, and the ramp
rate timer begins to count down to 1. When the ramp rate timer
completes a cycle, the RAM address generator increments to the
next address, and the timer reloads the ramp rate bits and
continues counting down. This sequence continues until the
RAM address generator has incremented to an address equal to
the RAM segment final address bits of the current RSCW. Upon
reaching this terminal address, the RAM address generator will
decrement in value at the ramp rate until it reaches the RAM
segment beginning address. Upon reaching the beginning
address, the entire sequence repeats.
The entire sequence repeats for as long as the part is
programmed for this mode. The no-dwell bit is a Don’t Care in
this mode. In general, this mode is identical in control to the
bidirectional ramp mode except the ramp up and down is
automatic (no external control via the Profile<0> input) and
switching profiles is valid. Once in this mode, the address
generator ramps from the beginning address to the final
address, then back to the beginning address at the rate
programmed into the ramp rate register. This mode enables
generation of an automatic saw tooth sweep characteristic.
Continuous Recirculate Mode
Continuous recirculate mode allows the AD9953 to offer
an automatic, continuous unidirectional sweep between two
frequencies. The AD9953 is programmed for continuous
recirculate mode by writing the RAM enable bit true and the RAM
mode control bits of each profile to be used to Logic 100(b).
Upon entering this mode (via an I/O UPDATE or changing
Profile<1:0>), the RAM address generator loads the RAM
segment beginning address bits of the current RSCW and the
ramp rate timer loads the RAM segment address ramp rate b
The RAM drives data from the beginning address, and
ra
c
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9954 | 制造商:AD 制造商全称:Analog Devices 功能描述:400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer |
| AD9954/PCB | 制造商:Analog Devices 功能描述:AD9954 400 MSPS DDS W/ 14 BIT DAC EVALBD - Bulk 制造商:Analog Devices 功能描述:EVALUATION KIT ((NS)) |
| AD9954/PCBZ | 功能描述:BOARD EVAL FOR 9954 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:AgileRF™ 标准包装:1 系列:PSoC® 主要目的:电源管理，热管理 嵌入式:- 已用 IC / 零件:- 主要属性:- 次要属性:- 已供物品:板，CD，电源 |
| AD9954/PCBZ1 | 制造商:AD 制造商全称:Analog Devices 功能描述:400 MSPS, 14-Bit, 1.8 V CMOS, Direct Digital Synthesizer |
| AD9954_09 | 制造商:AD 制造商全称:Analog Devices 功能描述:400 MSPS, 14-Bit, 1.8 V CMOS, Direct Digital Synthesizer |
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