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参数资料
| 型号： | AD9985AKSTZ-140 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/32页 |
| 文件大小： | 0K |
| 描述： | IC INTERFACE 8BIT 140MSPS 80LQFP |
| 标准包装： | 90 |
| 应用： | 视频 |
| 接口： | 串行 |
| 电源电压： | 2.2 V ~ 3.45 V |
| 封装/外壳： | 80-LQFP |
| 供应商设备封装： | 80-LQFP（14x14） |
| 包装： | 管件 |
| 安装类型： | 表面贴装 |
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AD9985
Rev. 0 | Page 16 of 32
disappear. In other systems, such as those that employ
Composite Sync (Csync) signals or embedded Sync-on-Green
(SOG), Hsync includes equalization pulses or other distortions
during Vsync. To avoid upsetting the clock generator during
Vsync, it is important to ignore these distortions. If the pixel
clock PLL sees extraneous pulses, it will attempt to lock to this
new frequency, and will have changed frequency by the end of
the Vsync period. It will then take a few lines of correct Hsync
timing to recover at the beginning of a new frame, resulting in a
“tearing” of the image at the top of the display.
The COAST input is provided to eliminate this problem. It is an
asynchronous input that disables the PLL input and allows the
clock to free-run at its then-current frequency. The PLL can
free-run for several lines without significant frequency drift.
.
P0
P1
P2
P3
P4
P5
P6
P7
5-PIPE DELAY
D0
D1
D2
D3
D4
D5
D6
D7
RGBIN
HSYNC
PxCK
HS
ADCCK
DATACK
DOUTA
HSOUT
VARIABLE DURATION
04799-
0-
010
Figure 10. 4:4:4 Mode (For RGB and YUV)
P0
P1
P2
P3
P4
P5
P6
P7
5-PIPE DELAY
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
RGBIN
HSYNC
PxCK
HS
ADCCK
DATACK
GOUTA
HSOUT
U0
V1
U2
V3
U4
V5
U6
V7
ROUTA
VARIABLE DURATION
04799-
0-
011
Figure 11. 4:2:2 Mode (For YUV Only)
2-WIRE SERIAL REGISTER MAP
The AD9985 is initialized and controlled by a set of registers, that determine the operating modes. An external controller is employed to
write and read the control registers through the two-line serial interface port.
Table 10. Control Register Map
Hex
Address
Write and
Read or
Read Only
Bits
Default
Value
Register Name
Function
00H
RO
7:0
Chip Revision
An 8-bit register that represents the silicon revision level.
01H*
R/W
7:0
01101001
PLL Div MSB
This register is for Bits [11:4] of the PLL divider. Greater values mean
the PLL operates at a faster rate. This register should be loaded first
whenever a change is needed. This will give the PLL more time to lock.
02H*
R/W
7:4
1101****
PLL Div LSB
Bits [7:4] of this word are written to the LSBs [3:0] of the PLL divider
word.
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