参数资料
型号: ADA4062-4ARUZ
厂商: Analog Devices Inc
文件页数: 8/20页
文件大小: 0K
描述: IC OPAMP JFET 1.4MHZ QD 14TSSOP
标准包装: 96
放大器类型: J-FET
电路数: 4
转换速率: 3.3 V/µs
增益带宽积: 1.4MHz
电流 - 输入偏压: 2pA
电压 - 输入偏移: 750µV
电流 - 电源: 165µA
电流 - 输出 / 通道: 20mA
电压 - 电源,单路/双路(±): 8 V ~ 36 V,±4 V ~ 18 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 14-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 14-TSSOP
包装: 管件
产品目录页面: 768 (CN2011-ZH PDF)
ADA4062-2/ADA4062-4
Rev. B | Page 16 of 20
PHASE REVERSAL
Phase reversal occurs in some amplifiers when the input common-
mode voltage range is exceeded. When the voltage driving the
input to these amplifiers exceeds the maximum input common-
mode voltage range, the output of the amplifiers changes polarity.
Most JFET input amplifiers have phase reversal if either input
exceeds the input common-mode range.
For the ADA4062-x, the output does not phase reverse if one
or both of the inputs exceeds the input voltage range but remains
within the positive supply rail and 0.5 V above the negative
supply rail. In other words, for an application with a supply
voltage of ±15 V, the input voltage can be as high as +15 V
without any output phase reversal. However, when the voltage
of the inputs is driven beyond 14.5 V, phase reversal occurs
due to saturation of the input stage leading to forward biasing
of the gate-drain diode. Phase reversal in ADA4062-x can be
prevented by using a Schottky diode to clamp the input terminals
to each other. In the simple buffer circuit in Figure 63, D1
protects the op amp against phase reversal, and R limits the
input current that flows into the op amp.
+VSY
–VSY
VO
07
67
0-
05
3
R
10k
ADA4062-x
D1
IN5711
Figure 63. Phase Reversal Solution Circuit
07
67
0-
0
63
TIME (40s/DIV)
VO
LT
AG
E
(
5V
/DI
V
)
VSY = ±15V
VOUT
VIN
Figure 64. No Phase Reversal
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