参数资料
型号: ADA4096-2WARMZ-R7
厂商: Analog Devices Inc
文件页数: 7/20页
文件大小: 0K
描述: IC OPAMP GP RRIO 8MSOP
标准包装: 1,000
放大器类型: 通用
电路数: 2
输出类型: 满摆幅
转换速率: 0.4 V/µs
增益带宽积: 786kHz
-3db带宽: 152kHz
电流 - 输入偏压: 3nA
电压 - 输入偏移: 35µV
电流 - 电源: 60µA
电流 - 输出 / 通道: 10mA
电压 - 电源,单路/双路(±): 3 V ~ 30 V,±1.5 V ~ 15 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 8-TSSOP,8-MSOP(0.118",3.00mm 宽)
供应商设备封装: 8-MSOP
包装: 带卷 (TR)
Data Sheet
ADA4096-2
Rev. A | Page 15 of 20
THEORY OF OPERATION
INPUT STAGE
09241-
045
R6
VCC
+IN
–IN
VEE
OVP
OUT
R7
D10
Q20
Q19
D11
Q16
D7
Q15
D8
Q14
Q17
Q10
Q13
Q18
D9
×1
I3
R2
R1
R3
R4
C2
Q12
D6
R5
Q9
Q11
Q6
Q8
Q7
Q5
Q4
Q3
Q1
Q2
I2
I1
C1
D3
D1
D4
D2
Figure 45. Simplified Schematic
Figure 45 shows a simplified schematic of the ADA4096-2. The
input stage comprises two differential pairs (Q1 to Q4 and Q5
to Q8) operating in parallel. When the input common-mode
voltage approaches VCC 1.5 V, Q1 to Q4 shut down as I1 reaches
its minimum voltage compliance. Conversely, when the input
common-mode voltage approaches VEE + 1.5 V, Q5 to Q8 shut
down as I2 reaches its minimum voltage compliance. This
topology allows for maximum input dynamic range because the
amplifier can function with its inputs at 200 mV outside the rail
(at room temperature).
As with any rail-to-rail input amplifier, VOS mismatch between
the two input pairs determines the CMRR of the amplifier. If
the input common-mode voltage range is kept within 1.5 V of
each rail, transitions between the input pairs are avoided, thus
improving the CMRR by approximately 10 dB (see Table 3 and
PHASE INVERSION
Some single-supply amplifiers exhibit phase inversion when
the input signal extends beyond the common-mode voltage
range of the amplifier. When the input devices become saturated,
the inverting and noninverting inputs exchange functions,
causing the output to move in the opposing direction.
Although phase inversion persists for only as long as the inputs are
saturated, it can be detrimental to applications where the amplifier
is part of a closed-loop system. The ADA4096-2 is free from phase
inversion over the entire common-mode voltage range, as well as
the overvoltage protected range stated in the Absolute Maximum
unity-gain configuration with the input signal at ±40 V and the
amplifier supplies at ±10 V.
CH1 10.0V
CH2 10.0V
M2.00ms
A CH1
–3.6V
T
34.20%
1
T
09241-
046
Figure 46. No Phase Reversal
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