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参数资料
| 型号： | ADA4410-6ACPZ-R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 5/16页 |
| 文件大小： | 0K |
| 描述： | IC VIDEO FILTER SELECT 32-LFCSP |
| 标准包装： | 1,500 |
| 类型： | 视频滤波器 |
| 应用： | 录音机，机顶盒 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-VQ（5x5） |
| 包装： | 带卷 (TR) |
ADA4410-6
Rev. B | Page 13 of 16
APPLICATIONS
OVERVIEW
With its high impedance multiplexed inputs and high output
drive, the ADA4410-6 is ideally suited to video reconstruction
and antialias filtering applications. The high impedance inputs
give designers flexibility with regard to how the input signals
are terminated. Devices with DAC current source outputs that
feed the ADA4410-6 can be loaded in whatever resistance
provides the best performance, and devices with voltage outputs
can be optimally terminated as well. The ADA4410-6 outputs
can each drive up to two source-terminated 75 Ω loads and can
therefore directly drive the outputs from set-top boxes, DVD
players, and the like without the need for a separate output buffer.
Binary control inputs are provided to select cutoff frequency,
throughput gain, and input signal. These inputs are compatible
with 3 V and 5 V TTL and CMOS logic levels, referenced to
GND. The disable feature is asserted by pulling the DISABLE
pin to the positive supply.
The LEVEL1 and LEVEL2 inputs comprise a differential input
that controls the dc level at the output pins.
MULTIPLEXER SELECT INPUTS
Selection between the two multiplexer inputs is controlled by
the logic signals applied to the MUX_SD and MUX_HD inputs.
The MUX_SD input controls the standard definition (SD)
inputs, and the MUX_HD input controls the high definition
(HD) inputs. Table 6 summarizes the multiplexer operation.
THROUGHPUT GAIN
The throughput gain of the ADA4410-6 signal paths can be ×2
or ×4. Gain selection is controlled by the logic signal applied to
the G_SEL pin. Table 6 summarizes how the gain is selected.
Composite Video Path Gain
The composite video signal is produced by passively summing
the C and V outputs (see Figure 1), which have been amplified
by their respective gain stages. Each signal experiences a 6 dB
loss as it passes through the passive summer and is subsequently
amplified by 6 dB in the fixed ×2 stage following the summer.
The net signal gain through the composite video path is therefore
0 dB, and the resulting composite signal present at the ADA4410-6
output is the sum of Y and C with unity gain. The offset voltage
at the composite video output is twice that of the offset on the Y
or C outputs because the offsets on the Y and C outputs are the
same and appear as a common-mode input to the summer. The
voltage between the summing resistors due to the offset voltages
is therefore equal to the output offset voltage on the Y and C
outputs and appears at the composite video output with a gain
of 2 after passing through the fixed ×2 gain stage.
DISABLE
The ADA4410-6 includes a disable feature that can be used to
save power when a particular device is not in use. As indicated
in the Overview section, the disable feature is asserted by pulling
the DISABLE pin to the positive supply. Table 6 summarizes the
disable feature operation. The DISABLE pin also functions as a
reference level for the logic inputs and, therefore, must be
connected to ground when the device is not disabled.
Table 6. Logic Pin Function Description
DISABLE
MUX_HD
MUX_SD
G_SEL
VS+ =
Disabled
1 = HD Channel 1
Selected
1 = SD Channel 1
Selected
1 = ×4
Gain
GND =
Enabled
0 = HD Channel 2
Selected
0 = SD Channel 2
Selected
0 = ×2
Gain
CUTOFF FREQUENCY SELECTION
Four combinations of cutoff frequencies are provided for the
HD video signals. The cutoff frequencies were selected to
correspond with the most commonly deployed HD scanning
systems. Selection between the cutoff frequency combinations is
controlled by the logic signals applied to the F_SEL_A and
F_SEL_B inputs. Table 7 summarizes cutoff frequency selection.
Table 7. Filter Cutoff Frequency Selection
F_SEL_A
F_SEL_B
Y/G Cutoff
Pb/B Cutoff
Pr/R Cutoff
0
36 MHz
0
1
36 MHz
18 MHz
1
0
18 MHz
1
9 MHz
OUTPUT DC OFFSET CONTROL
The LEVEL1 and LEVEL2 inputs work as a differential input-
referred output offset control. In other words, the output offset
voltage of a given channel (with the exception of the CV
channel) is equal to the difference in voltage between the
LEVEL1 and LEVEL2 inputs multiplied by the overall filter
gain. This relationship is expressed in Equation 1.
VOS (OUT) = (LEVEL1 LEVEL2)(G)
(1)
where:
LEVEL1 and LEVEL2 are the voltages applied to the respective
inputs.
G is throughput gain.
For example, with the G_SEL input set for ×2 gain, setting
LEVEL1 to 300 mV and LEVEL2 to 0 V shifts the offset voltages
at the ADA4410-6 outputs to 600 mV. This particular setting
can be used in most single-supply applications to keep the
output swings safely above the negative supply rail.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADA4410-6ACPZR7KL1 | 制造商:Analog Devices 功能描述: |
| ADA4410-6ACPZ-RL | 功能描述:IC VIDEO FILTER SELECT 32-LFCSP RoHS:是 类别:集成电路 (IC) >> 线性 - 视频处理 系列:- 产品变化通告:Product Discontinuation 07/Mar/2011 标准包装:3,000 系列:OMNITUNE™ 类型:调谐器 应用:移动电话，手机，视频显示器 安装类型:表面贴装 封装/外壳:65-WFBGA 供应商设备封装:PG-WFSGA-65 包装:带卷 (TR) 其它名称:SP000365064 |
| ADA4411-3 | 制造商:AD 制造商全称:Analog Devices 功能描述:Integrated Triple Video Filter and Buffer with Selectable Cutoff Frequencies and Multiplexed Inputs for RGB, HD/SD |
| ADA4411-3ARQZ | 功能描述:IC HD/FILTER/BUFFER/MUX 24QSOP RoHS:是 类别:集成电路 (IC) >> 线性 - 放大器 - 视频放大器和频缓冲器 系列:- 标准包装:1,000 系列:- 应用:驱动器 输出类型:差分 电路数:3 -3db带宽:350MHz 转换速率:1000 V/µs 电流 - 电源:14.5mA 电流 - 输出 / 通道:60mA 电压 - 电源，单路/双路(±):5 V ~ 12 V，±2.5 V ~ 6 V 安装类型:表面贴装 封装/外壳:20-VFQFN 裸露焊盘 供应商设备封装:20-QFN 裸露焊盘（4x4） 包装:带卷 (TR) |
| ADA4411-3ARQZ-R7 | 功能描述:IC HD/FILTER/BUFFER/MUX 24QSOP RoHS:是 类别:集成电路 (IC) >> 线性 - 放大器 - 视频放大器和频缓冲器 系列:- 标准包装:1,000 系列:- 应用:驱动器 输出类型:差分 电路数:3 -3db带宽:350MHz 转换速率:1000 V/µs 电流 - 电源:14.5mA 电流 - 输出 / 通道:60mA 电压 - 电源，单路/双路(±):5 V ~ 12 V，±2.5 V ~ 6 V 安装类型:表面贴装 封装/外壳:20-VFQFN 裸露焊盘 供应商设备封装:20-QFN 裸露焊盘（4x4） 包装:带卷 (TR) |
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