参数资料
型号: ADA4817-1ARDZ-R7
厂商: Analog Devices Inc
文件页数: 10/28页
文件大小: 0K
描述: IC OPAMP VF 410MHZ LN 40MA 8SOIC
标准包装: 1,000
系列: FastFET™
放大器类型: 电压反馈
电路数: 1
转换速率: 870 V/µs
增益带宽积: 410MHz
-3db带宽: 1.05GHz
电流 - 输入偏压: 2pA
电压 - 输入偏移: 400µV
电流 - 电源: 19mA
电流 - 输出 / 通道: 40mA
电压 - 电源,单路/双路(±): 5 V ~ 10 V,±2.5 V ~ 5 V
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm Width)裸露焊盘
供应商设备封装: 8-SOIC-EP
包装: 带卷 (TR)
ADA4817-1/ADA4817-2
Data Sheet
Rev. B | Page 18 of 28
LEAKAGE CURRENTS
Poor PCB layout, contaminants, and the board insulator
material can create leakage currents that are much larger than
the input bias current of the ADA4817-1/ADA4817-2. Any
voltage differential between the inputs and nearby runs sets
up leakage currents through the PCB insulator, for example, 1 V/
100 G = 10 pA. Similarly, any contaminants, such as skin oils
on the board, can create significant leakage. To reduce leakage
significantly, put a guard ring (shield) around the inputs and
input leads that are driven to the same voltage potential as the
inputs. This way there is no voltage potential between the inputs
and surrounding area to set up any leakage currents. For the
guard ring to be completely effective, it must be driven by a
relatively low impedance source and should completely
surround the input leads on all sides (above and below)
while using a multilayer board.
Another effect that can cause leakage currents is the charge
absorption of the insulator material itself. Minimizing the amount
of material between the input leads and the guard ring helps to
reduce the absorption. In addition, low absorption materials,
such as Teflon or ceramic, can be necessary in some instances.
INPUT CAPACITANCE
Along with bypassing and ground, high speed amplifiers can be
sensitive to parasitic capacitance between the inputs and ground. A
few picofarads of capacitance reduces the input impedance at high
frequencies, in turn increasing the gain of the amplifier, causing
peaking of the frequency response or even oscillations if severe
enough. It is recommended that the external passive components
connected to the input pins be placed as close as possible to the
inputs to avoid parasitic capacitance. The ground and power
planes must be kept at a small distance from the input pins on
all layers of the board.
INPUT-TO-INPUT/OUTPUT COUPLING
To minimize capacitive coupling between the inputs and outputs,
the output signal traces should not be parallel with the inputs.
In addition, the input traces should not be close to each other. A
minimum of 7 mils between the two inputs is recommended.
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