参数资料
型号: ADA4856-3YCPZ-RL
厂商: Analog Devices Inc
文件页数: 4/20页
文件大小: 0K
描述: IC AMP 3CH RRO VFB G=+2 16LFCSP
标准包装: 5,000
应用: 电压反馈
输出类型: 满摆幅
电路数: 3
-3db带宽: 370MHz
转换速率: 800 V/µs
电流 - 电源: 7.8mA
电流 - 输出 / 通道: 52mA
电压 - 电源,单路/双路(±): 3 V ~ 5.5 V,±1.5 V ~ 2.75 V
安装类型: 表面贴装
封装/外壳: 16-VQFN 裸露焊盘,CSP
供应商设备封装: 16-LFCSP-VQ EP(4x4)
包装: 带卷 (TR)
ADA4856-3
Data Sheet
Rev. B | Page 12 of 20
THEORY OF OPERATION
The ADA4856-3 is a voltage feedback op amp that employs a
new input stage that achieves a high slew rate while maintaining
a wide common-mode input range. The input common-mode
range of the ADA4856-3 extends from 200 mV below the negative
rail to about 1 V from the positive rail. This feature makes the
ADA4856-3 ideal for low voltage single-supply applications. In
addition, this new input stage does not sacrifice noise performance
for slew rate. At 14 nV/√Hz, the ADA4856-3 is one of the
lowest noise rail-to-rail output video amplifiers in the market.
Besides a novel input stage, the ADA4856-3 employs the Analog
Devices, Inc., patented rail-to-rail output stage. This output
stage makes an efficient use of the power supplies, allowing the
op amp to drive up to three video loads to within 300 mV from
both rails. In addition, this output stage provides the amplifier
with very fast overdrive characteristics, an important property
in video applications.
The ADA4856-3 comes in a 16-lead LFCSP that has an exposed
thermal pad for lower operating temperature. This pad is connected
internally to the negative rail. To avoid printed circuit board (PCB)
layout problems, the ADA4856-3 features a new pinout flow that
is optimized for video applications. As shown in Figure 4, the
feedback and gain resistors are on-chip, which minimizes the
number of components needed and improves the design layout.
The ADA4856-3 is fabricated in Analog Devices dielectrically
isolated eXtra Fast Complementary Bipolar 3 (XFCB3) process,
which results in the outstanding speed and dynamic range
displayed by the amplifier.
OUT
+IN
–IN
C
C1
–VS
Gm1
Gm2
+VS
R
07686-
147
Figure 33. High Level Design Schematic
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