参数资料
型号: ADAU1781BCPZ-RL7
厂商: Analog Devices Inc
文件页数: 1/92页
文件大小: 0K
描述: IC SIGMADSP CODEC LN 32LFCSP
标准包装: 1,500
系列: SigmaDSP®
类型: 立体声音频
数据接口: I²C,串行,SPI?
分辨率(位): 24 b
ADC / DAC 数量: 2 / 2
三角积分调变:
S/N 比,标准 ADC / DAC (db): 100 / 105(差分),100 / 103(单端)
动态范围,标准 ADC / DAC (db): 99.2 / 105(差分),99.2 / 103(单端)
电压 - 电源,模拟: 1.8 V ~ 3.65 V
电压 - 电源,数字: 1.63 V ~ 3.65 V
工作温度: -25°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘,CSP
供应商设备封装: 32-LFCSP-VQ
包装: 带卷 (TR)
Low Noise Stereo Codec with
SigmaDSP Processing Core
ADAU1781
Rev. B
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responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
2009–2011 Analog Devices, Inc. All rights reserved.
FEATURES
24-bit stereo audio ADC and DAC
400 mW speaker amplifier (into 8 load)
Programmable SigmaDSP audio processing core
Wind noise detection and filtering
Enhanced stereo capture (ESC)
Dynamics processing
Equalization and filtering
Volume control and mute
Sampling rates from 8 kHz to 96 kHz
Stereo pseudo differential microphone input
Optional stereo digital microphone input pulse-density
modulation (PDM)
Stereo line output
PLL supporting a range of input clock rates
Analog and digital I/O 1.8 V to 3.3 V
Software control via SigmaStudio graphical user interface
Software-controllable, clickless mute
Software register and hardware pin standby mode
32-lead, 5 mm × 5 mm LFCSP
APPLICATIONS
Digital still cameras
Digital video cameras
GENERAL DESCRIPTION
The ADAU1781 is a low power, 24-bit stereo audio codec. The
low noise DAC and ADC support sample rates from 8 kHz to
96 kHz. Low current draw and power saving modes make the
ADAU1781 ideal for battery-powered audio applications.
A programmable SigmaDSP core provides enhanced record
and playback processing to improve overall audio quality.
The record path includes two digital stereo microphone inputs
and an analog stereo input path. The analog inputs can be
configured for either a pseudo differential or a single-ended
stereo source. A dedicated analog beep input signal can be
mixed into any output path. The ADAU1781 includes a stereo
line output and speaker driver, which makes the device capable of
supporting dynamic speakers.
The serial control bus supports the I2C or SPI protocols, and
the serial audio bus is programmable for I2S, left-justified, right-
justified, or TDM mode. A programmable PLL supports flexible
clock generation for all standard rates and available master clocks
from 11 MHz to 20 MHz.
FUNCTIONAL BLOCK DIAGRAM
PGA
LEFT
ADC
RIGHT
ADC
LEFT
DAC
RIGHT
DAC
PGA
BEEP
PDN
MICBIAS
LMIC/LMICN/
MICD1
LMICP
RMIC/RMICN/
MICD2
RMICP
AOUTL
AOUTR
SPP
SPN
PLL
SigmaDSP CORE
WIND NOISE
NOTCH FILTER
EQUALIZER
DIGITAL VOLUME
CONTROL
DYNAMIC
PROCESSING
OUTPUT
MIXER
M
CKI
REGULATOR
CM
IOV
D
DG
ND
DV
DDO
UT
AV
DD1
AG
ND1
AV
DD2
AG
ND2
SERIAL DATA
INPUT/OUTPUT PORTS
ADC_S
DAT
A/
GP
IO1
B
C
LK
/GP
IO2
LR
C
LK
/GP
IO3
DAC_S
DAT
A/
GP
IO0
I2C/SPI
CONTROL PORT
ADDR0/
CDAT
A
ADDR1/
CL
AT
CH
S
CL
/CCL
K
S
DA/
CO
UT
ADAU1781
MICROPHONE
BIAS
08314-
001
Figure 1.
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