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| 型号： | ADC08032 |
| 厂商： | National Semiconductor Corporation |
| 元件分类： | 串行ADC |
| 英文描述： | 8-Bit High-Speed Serial I/O A/D Converters with Multiplexer Options, Voltage Reference, and Track/Hold Function(8位高速串行输入/输出A/D转换器带多路选择，电压基准和跟踪/保持功能) |
| 中文描述： | 8位高速串行I /办公自动化/ D的多路复用器选项，电压参考，并跟踪转换器/保持功能（8位高速串行输入/输出的A / D转换器带多路选择，电压基准和跟踪/保持功能） |
| 文件页数： | 13/24页 |
| 文件大小： | 552K |
| 代理商： | ADC08032 |
Functional Description
(Continued)
3.
When the start bit has been shifted into the start location
of the MUX register, the input channel has been as-
signed and a conversion is about to begin. An interval of
1
2
clock period (where nothing happens) is automatically
inserted to allow the selected MUX channel to settle.
The SARS line goes high at this time to signal that a con-
version is now in progress and the DI line is disabled (it
no longer accepts data).
The data out (DO) line now comes out of TRI-STATE
and provides a leading zero for this one clock period of
MUX settling time.
During the conversion the output of the SAR comparator
indicates whether the analog input is greater than (high)
or less than (low) a series of successive voltages gener-
ated internally from a ratioed capacitor array (first 5 bits)
and a resistor ladder (last 3 bits). After each comparison
the comparator’s output is shipped to the DO line on the
falling edge of CLK. This data is the result of the conver-
sion being shifted out (with the MSB first) and can be
read by the processor immediately.
After 8 clock periods the conversion is completed. The
SARS line returns low to indicate this
1
2
clock cycle later.
4.
5.
6.
7.
The stored data in the successive approximation register
is loaded into an internal shift register. If the programmer
prefers the data can be provided in an LSB first format
[this makes use of the shift enable (SE) control line]. On
theADC08038 the SE line is brought out and if held high
the value of the LSB remains valid on the DO line. When
SE is forced low the data is clocked out LSB first. On de-
vices which do not include the SE control line, the data,
LSB first, is automatically shifted out the DO line after
the MSB first data stream. The DO line then goes low
and stays low until CS is returned high. The ADC08031
is an exception in that its data is only output in MSB first
format.
All internal registers are cleared when the CS line is high
and the t
requirement is met. See Data Input Tim-
ing under Timing Diagrams. If another conversion is de-
sired CS must make a high to low transition followed by
address information.
The DI and DO lines can be tied together and controlled
through a bidirectional processor I/O bit with one wire.
This is possible because the DI input is only “looked-at”
during the MUX addressing interval while the DO line is
still in a high impedance state.
8.
8 Single-Ended
DS010555-48
8 Pseudo-Differential
DS010555-49
4 Differential
DS010555-50
Mixed Mode
DS010555-51
FIGURE 1. Analog Input Multiplexer Options for the ADC08038
A
www.national.com
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| ADC08032CIWM | 功能描述:IC ADC 8BIT HS SERIAL I/O 14SOIC RoHS:否 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:12 采样率（每秒）:3M 数据接口:- 转换器数目:- 功率耗散（最大）:- 电压电源:- 工作温度:- 安装类型:表面贴装 封装/外壳:SOT-23-6 供应商设备封装:SOT-23-6 包装:带卷 (TR) 输入数目和类型:- |
| ADC08032CIWMX | 功能描述:IC ADC 8BIT HS SERIAL I/O 14SOIC RoHS:否 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:12 采样率（每秒）:3M 数据接口:- 转换器数目:- 功率耗散（最大）:- 电压电源:- 工作温度:- 安装类型:表面贴装 封装/外壳:SOT-23-6 供应商设备封装:SOT-23-6 包装:带卷 (TR) 输入数目和类型:- |
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