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参数资料
| 型号： | ADC0811 |
| 厂商： | National Semiconductor Corporation |
| 英文描述： | 8-Bit Serial I/O A/D Converter With 11-Channel Multiplexer |
| 中文描述： | 8位串行I /办公自动化/ D转换器11通道多路复用器 |
| 文件页数： | 9/14页 |
| 文件大小： | 323K |
| 代理商： | ADC0811 |
Functional Description
1.0 DIGITAL INTERFACE
The ADC0811 uses five input/output pins to implement the
serial interface. Taking chip select (CS) low enables the I/O
data lines (DO and DI) and the serial clock input (S
CLK
). The
result of the last conversion is transmitted by the A/D on the
DO line, while simultaneously the DI line receives the ad-
dress data that selects the mux channel for the next conver-
sion. The mux address is shifted in on the rising edge of
S
CLK
and the conversion data is shifted out on the falling
edge. It takes eight S
CLK
cycles to complete the serial I/O.
A second clock (
w
2
) controls the SAR during the conversion
process and must be continuously enabled.
1.1 CONTINUOUS S
CLK
With a continuous S
CLK
input CS must be used to synchro-
nize the serial data exchange (seeFigure 1). The ADC0811
recognizes a valid CS one to three
w
2
clock periods after
the actual falling edge of CS. This is implemented to ensure
noise immunity of the CS signal. Any spikes on CS less than
one
w
2
clock period will be ignored. CS must remain low
during the complete I/O exchange which takes eight S
CLK
cycles. Although CS is not immediately acknowledged for
the purpose of starting a new conversion, the falling edge of
CS immediately enables DO to output the MSB (D7) of the
previous conversion.
The first S
CLK
rising edge will be acknowledged after a set-
up time (t
set-up
) has elapsed from the falling edge of CS.
This and the following seven S
CLK
rising edges will shift in
thechanneladdressfortheanalogmultiplexer.Sincethereare
12 channels only four address bits are utilized. The first four
S
CLK
cycles clock in the mux address, during the next four
S
CLK
cyclestheanaloginputisselectedandsampled.During
this mux address/sample cycle, data from the last conver-
sion is also clocked out on DO. Since D7 was clocked out
on the falling edge of CS only data bits D6–D0 remain to be
received. The following seven falling edges of S
CLK
shift out
this data on DO.
The 8th S
CLK
falling edge initiates the beginning of the A/D’s
actual conversion process which takes between 48 to 64
w
2
cycles (T
C
). During this time CS can go high to TRI-STATE
DO and disable the S
CLK
input or it can remain low. If CS is
held low a new I/O exchange will not start until the conver-
sion sequence has been completed, however once the con-
version ends serial I/O will immediately begin. Since there is
an ambiguity in the conversion time (T
C
) synchronizing the
data exchange is impossible. Therefore CS should go high
before the 48th
w
2
clock has elasped and return low after
the 64th
w
2
to synchronize serial communication.
A conversion or I/O operation can be aborted at any time by
strobing CS. If CS is high or low less than one
w
2
clock it will
be ignored by the A/D. If the CS is strobed high or low
between 1 to 3
w
2
clocks the A/D may or may not respond.
Therefore CS must be strobed high or low greater than 3
w
2
clocks to ensure recognition. If a conversion or I/O ex-
change is aborted while in process the consequent data
output will be erroneous until a complete conversion se-
quence has been implemented.
1.2 DISCONTINUOUS S
CLK
Another way to accomplish synchronous serial communica-
tion is to tie CS low continuously and disable S
CLK
after its
8th falling edge (see Figure 2). S
CLK
must remain low for
TL/H/5587–18
FIGURE 1
TL/H/5587–19
FIGURE 2
9
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