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参数资料
| 型号： | ADC0820 |
| 厂商： | National Semiconductor Corporation |
| 英文描述： | 8-Bit High Speed μP Compatible A/D Converter with Track/Hold Function(8位高速μP兼容A/D转换器带跟踪/保持功能) |
| 中文描述： | CMOS、高速、8位A/D转换器，带有采样/保持功能 |
| 文件页数： | 5/22页 |
| 文件大小： | 472K |
| 代理商： | ADC0820 |
AC Electrical Characteristics
(Continued)
The following specifications apply for V
CC
=5V, t
r
=t
f
=20 ns, V
REF
(+)=5V, V
REF
()=0V and T
A
=25C unless otherwise speci-
fied.
Typ
Tested
Limit
(Note 7)
Design
Limit
(Note 8)
Parameter
Conditions
(Note 6)
Units
t
ACC2
, Access Time (Delay from
Falling Edge of RD to Output
Valid)
Pin 7 = V
CC
, t
RD
>
t
I
; Figure 4
C
L
=15 pF
C
L
=100 pF
R
PULLUP
= 1k and C
L
= 15 pF
70
90
30
120
150
ns
ns
ns
t
ACC3
, Access Time (Delay from
Rising Edge of RDY to Output
Valid)
t
I
, Internal Comparison Time
Pin 7=V
CC
; Figures 4, 5
C
L
=50 pF
R
L
=1k, C
L
=10 pF
800
1300
ns
t
1H
, t
0H
, TRI-STATE Control
(Delay from Rising Edge of RD to
Hi-Z State)
t
INTL
, Delay from Rising Edge of
WR to Falling Edge of INT
100
200
ns
Pin 7 = V
CC
, C
L
= 50 pF
t
RD
>
t
I
; Figure 4
t
RD
<
t
I
; Figure 3
Figures 2, 3, 4
C
L
=50 pFc
Figure 5 C
L
=50 pF
t
I
ns
ns
ns
t
RD
+200
125
t
RD
+290
225
t
INTH
, Delay from Rising Edge of
RD to Rising Edge of INT
t
INTHWR
, Delay from Rising Edge of
WR to Rising Edge of INT
t
RDY
, Delay from CS to RDY
t
ID
, Delay from INT to Output Valid
t
RI
, Delay from RD to INT
175
270
ns
Figure 2 C
L
=50 pF, Pin 7 =0
Figure 5
Pin 7=V
CC
, t
RD
<
t
I
Figure 3
Figures 2, 3, 4, 5
(Note 4) See Graph
50
20
200
100
50
290
ns
ns
ns
t
P
, Delay from End of Conversion
to Next Conversion
Slew Rate, Tracking
C
VIN
, Analog Input Capacitance
C
OUT
, Logic Output Capacitance
C
IN
, Logic Input Capacitance
500
ns
0.1
45
5
5
V/μs
pF
pF
pF
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2:
All voltages are measured with respect to the GND pin, unless otherwise specified.
Note 3:
Total unadjusted error includes offset, full-scale, and linearity errors.
Note 4:
Accuracy may degrade if t
WR
or t
RD
is shorter than the minimum value specified. See Accuracy vs t
WR
and Accuracy vs t
RD
graphs.
Note 5:
When the input voltage (V
IN
) at any pin exceeds the power supply rails (V
IN
<
V
or V
IN
>
V
+
) the absolute value of current at that pin should be limited to
1 mA or less. The 4 mA package input current limits the number of pins that can exceed the power supply boundaries with a 1 mA current limit to four.
Note 6:
Typicals are at 25C and represent most likely parametric norm.
Note 7:
Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 8:
Design limits are guaranteed but not 100% tested. These limits are not used to calculate outgoing quality levels.
Note 9:
Human body model, 100 pF discharaged through a 1.5 k
resistor.
www.national.com
5
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