参数资料
型号: ADC082S101CIMM
厂商: NATIONAL SEMICONDUCTOR CORP
元件分类: ADC
英文描述: 2 Channel, 1 MSPS, 8-Bit A/D Converter
中文描述: 2-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8
封装: MSOP-8
文件页数: 16/19页
文件大小: 925K
代理商: ADC082S101CIMM
Applications Information
(Continued)
conversion, it is necessary to clock in the data indicating the
input that is selected for the conversion after the current one.
See
Tables 1, 2
and
Table 3
.
If CS and SCLK go low simultaneously, it is the following
rising edge of SCLK that is considered the first rising edge
for clocking data into DIN.
There are no power-up delays or dummy conversions re-
quired with the ADC082S101. The ADC is able to sample
and convert an input to full conversion immediately following
power up. The first conversion result after power-up will be
that of IN1.
TABLE 1. Control Register Bits
Bit 7 (MSB)
DONTC
Bit 6
DONTC
Bit 5
ADD2
Bit 4
ADD1
Bit 3
ADD0
Bit 2
DONTC
Bit 1
DONTC
Bit 0
DONTC
TABLE 2. Control Register Bit Descriptions
Bit #:
7 - 6, 2 - 0
Symbol:
DONTC
ADD0
ADD1
ADD2
Description
Don’t care. The value of these bits do not affect the device.
These bits determine which input channel will be sampled and converted in
the next track/hold cycle. The mapping between codes and channels is
shown in
Table 3
.
3
4
5
TABLE 3. Input Channel Selection
ADD2
x
x
x
ADD1
0
0
1
ADD0
0
1
x
Input Channel
IN1 (Default)
IN2
Not allowed. The output signal at the D
OUT
pin is indeterminate if ADD1 is high.
A
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