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参数资料
| 型号： | ADC082S101CIMMX |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | ADC |
| 英文描述： | 2 Channel, 1 MSPS, 8-Bit A/D Converter |
| 中文描述： | 2-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| 封装： | MSOP-8 |
| 文件页数： | 18/19页 |
| 文件大小： | 925K |
| 代理商： | ADC082S101CIMMX |
Applications Information
(Continued)
5.0 ANALOG INPUTS
An equivalent circuit for one of the ADC082S101’s input
channels is shown in
Figure 5
. Diodes D1 and D2 provide
ESD protection for the analog inputs. At no time should any
input go beyond (V
A
+ 300 mV) or (GND 300 mV), as these
ESD diodes will begin conducting, which could result in
erratic operation.
The capacitor C1 in
Figure 5
has a typical value of 3 pF, and
is mainly the package pin capacitance. Resistor R1 is the on
resistance of the multiplexer and track / hold switch, and is
typically 500 ohms. Capacitor C2 is the ADC082S101 sam-
pling capacitor and is typically 30 pF. The ADC082S101 will
deliver best performance when driven by a low-impedance
source to eliminate distortion caused by the charging of the
sampling capacitance. This is especially important when
using theADC082S101 to sampleAC signals.Also important
when sampling dynamic signals is a band-pass or low-pass
filter to reduce harmonics and noise, improving dynamic
performance.
6.0 DIGITAL INPUTS AND OUTPUTS
The ADC082S101’s digital output DOUT is limited by, and
cannot exceed, the supply voltage, V
A
. The digital input pins
are not prone to latch-up and, and although not recom-
mended, SCLK, CS and DIN may be asserted before V
A
without any latchup risk.
7.0 POWER SUPPLY CONSIDERATIONS
The ADC082S101 is fully powered-up whenever CS is low,
and fully powered-down whenever CS is high, with one
exception: the ADC082S101 automatically enters power-
down mode between the 16th falling edge of a conversion
and the 1st falling edge of the subsequent conversion (see
Timing Diagrams).
The ADC082S101 can perform multiple conversions back to
back; each conversion requires 16 SCLK cycles. The
ADC082S101 will perform conversions continuously as long
as CS is held low.
The user may trade off throughput for power consumption by
simply performing fewer conversions per unit time. The
Power Consumption vs. Sample Rate curve in the Typical
Performance Curves section shows the typical power con-
sumption of the ADC082S101 versus throughput. To calcu-
late the power consumption, simply multiply the fraction of
time spent in the normal mode by the normal mode power
consumption , and add the fraction of time spent in shutdown
mode multiplied by the shutdown mode power dissipation.
7.1 Power Management
When the ADC082S101 is operated continuously in normal
mode, the maximum throughput is f
SCLK
/16. Throughput
may be traded for power consumption by running f
SCLK
at its
maximum 16 MHz and performing fewer conversions per
unit time, putting the ADC082S101 into shutdown mode
between conversions. A plot of typical power consumption
versus throughput is shown in the Typical Performance
Curves section. To calculate the power consumption for a
given throughput, multiply the fraction of time spent in the
normal mode by the normal mode power consumption and
add the fraction of time spent in shutdown mode multiplied
by the shutdown mode power consumption. Generally, the
user will put the part into normal mode and then put the part
back into shutdown mode. Note that the curve of power
consumption vs. throughput is nearly linear. This is because
the power consumption in the shutdown mode is so small
that it can be ignored for all practical purposes.
7.2 Power Supply Noise Considerations
The charging of any output load capacitance requires cur-
rent from the power supply, V
. The current pulses required
from the supply to charge the output capacitance will cause
voltage variations on the supply. If these variations are large
enough, they could degrade SNR and SINAD performance
of the ADC. Furthermore, discharging the output capaci-
tance when the digital output goes from a logic high to a logic
low will dump current into the die substrate, which is resis-
tive. Load discharge currents will cause "ground bounce"
noise in the substrate that will degrade noise performance if
that current is large enough. The larger is the output capaci-
tance, the more current flows through the die substrate and
the greater is the noise coupled into the analog channel,
degrading noise performance.
To keep noise out of the power supply, keep the output load
capacitance as small as practical. If the load capacitance is
greater than 50 pF, use a 100
series resistor at the ADC
output, located as close to the ADC output pin as practical.
This will limit the charge and discharge current of the output
capacitance and improve noise performance.
20125414
FIGURE 5. Equivalent Input Circuit
A
www.national.com
18
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADC082S101CIMMX/NOPB | 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| ADC082S101EVAL | 功能描述:数据转换 IC 开发工具 ADC082S101 EVAL BOARD RoHS:否 制造商:Texas Instruments 产品:Demonstration Kits 类型:ADC 工具用于评估:ADS130E08 接口类型:SPI 工作电源电压:- 6 V to + 6 V |
| ADC083000 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:8-Bit, 3 GSPS, High Performance, Low Power A/D Converter |
| ADC083000_07 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:8-Bit, 3 GSPS, High Performance, Low Power A/D Converter |
| ADC083000_0705 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:8-Bit, 3 GSPS, High Performance, Low Power A/D Converter |
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