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参数资料
| 型号： | ADC082S101EVAL |
| 厂商： | National Semiconductor Corporation |
| 英文描述： | 2 Channel, 1 MSPS, 8-Bit A/D Converter |
| 中文描述： | 2通道，1 MSPS的，8位A / D转换器 |
| 文件页数： | 15/19页 |
| 文件大小： | 925K |
| 代理商： | ADC082S101EVAL |
Applications Information
1.0 ADC082S101 OPERATION
The ADC082S101 is a successive-approximation analog-to-
digital converter designed around a charge-redistribution
digital-to-analog converter. Simplified schematics of the
ADC082S101 in both track and hold modes are shown in
Figures 1, 2
, respectively. In
Figure 1
, the ADC082S101 is in
track mode: switch SW1 connects the sampling capacitor to
one of two analog input channels through the multiplexer,
and
SW2
balances
the
ADC082S101 is in this state for the first three SCLK cycles
after CS is brought low.
Figure 2
shows the ADC082S101 in hold mode: switch SW1
connects the sampling capacitor to ground, maintaining the
comparator
inputs.
The
sampled voltage, and switch SW2 unbalances the compara-
tor. The control logic then instructs the charge-redistribution
DAC to add fixed amounts of charge to the sampling capaci-
tor until the comparator is balanced. When the comparator is
balanced, the digital word supplied to the DAC is the digital
representation
of
the
analog
ADC082S101 is in this state for the fourth through sixteenth
SCLK cycles after CS is brought low.
The time when CS is low is considered a serial frame. Each
of these frames should contain an integer multiple of 16
SCLK cycles, during which time a conversion is performed
and clocked out at the DOUT pin and data is clocked into the
DIN pin to indicate the multiplexer address for the next
conversion.
input
voltage.
The
2.0 USING THE ADC082S101
AnADC082S101 timing diagram and a serial interface timing
diagram for the ADC082S101 are shown in the Timing Dia-
grams section. CS is chip select, which initiates conversions
and frames the serial data transfers. SCLK (serial clock)
controls both the conversion process and the timing of serial
data. DOUT is the serial data output pin, where a conversion
result is sent as a serial data stream, MSB first. Data to be
written to the ADC082S101’s Control Register is placed on
DIN, the serial data input pin. New data is written to DIN with
each conversion.
A serial frame is initiated on the falling edge of CS and ends
on the rising edge of CS. Each frame must contain an integer
multiple of 16 rising SCLK edges. The ADC output data
(DOUT) is in a high impedance state when CS is high and is
active when CS is low. Thus, CS acts as an output enable.
Additionally, the device goes into a power down state when
CS is high and also between continuous conversion cycles.
During the first 3 cycles of SCLK, the ADC is in the track
mode, acquiring the input voltage. For the next 13 SCLK
cycles the conversion is accomplished and the data is
clocked out, MSB first, starting with the 5th clock. If there is
more than one conversion in a frame, the ADC will re-enter
the track mode on the falling edge of SCLK after the N*16th
rising edge of SCLK, and re-enter the hold/convert mode on
the N*16+4th falling edge of SCLK, where "N" is an integer.
When CS is brought high, SCLK is internally gated off. If
SCLK is stopped in the low state while CS is high, the
subsequent fall of CS will generate a falling edge of the
internal version of SCLK, putting the ADC into the track
mode. This is seen by the ADC as the first falling edge of
SCLK. If SCLK is stopped with SCLK high, the ADC enters
the track mode on the first falling edge of SCLK after the
falling edge of CS.
During each conversion, data is clocked into the DIN pin on
the first 8 rising edges of SCLK after the fall of CS. For each
20125409
FIGURE 1. ADC082S101 in Track Mode
20125410
FIGURE 2. ADC082S101 in Hold Mode
A
www.national.com
15
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