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参数资料
| 型号： | ADC0844BCN |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | ADC |
| 英文描述： | 8-Bit uP Compatible A/D Converters with Multiplexer Options |
| 中文描述： | 4-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDIP20 |
| 封装： | 0.300 INCH, PLASTIC, DIP-20 |
| 文件页数： | 9/20页 |
| 文件大小： | 467K |
| 代理商： | ADC0844BCN |
Functional Description
The ADC0844 and ADC0848 contain a 4-channel and
8-channel analog input multiplexer (MUX) respectively. Each
MUX can be configured into one of three modes of operation
differential, pseudo-differential, and single ended. These
modes are discussed in the Applications Information Sec-
tion. The specific mode is selected by loading the MUX ad-
dress latch with the proper address (see Table 1 and Table
2). Inputs to the MUX address latch (MA0-MA4) are common
with data bus lines (DB0-DB4) and are enabled when the RD
line is high.Aconversion is initiated via the CS and WR lines.
If the data from a previous conversion is not read, the INTR
line will be low. The falling edge of WR will reset the INTR
line high and ready theA/D for a conversion cycle. The rising
edge of WR, with RD high, strobes the data on the MA0/
DB0-MA4/DB4 inputs into the MUX address latch to select a
new input configuration and start a conversion. If the RD line
is held low during the entire low period of WR the previous
MUX configuration is retained, and the data of the previous
conversion is the output on lines DB0-DB7. After the conver-
sion cycle (t
≤
40 μs), which is set by the internal clock fre-
quency, the digital data is transferred to the output latch and
the INTR is asserted low. Taking CS and RD low resets INTR
output high and outputs the conversion result on the data
lines (DB0-DB7).
Applications Information
1.0 MULTIPLEXER CONFIGURATION
The design of these converters utilizes a sampled-data com-
parator structure which allows a differential analog input to
be converted by a successive approximation routine.
The actual voltage converted is always the difference be-
tween an assigned “+” input terminal and a “” input terminal.
The polarity of each input terminal of the pair being con-
verted indicates which line the converter expects to be the
most positive. If the assigned “+” input is less than the “” in-
put the converter responds with an all zeros output code.
A unique input multiplexing scheme has been utilized to pro-
vide multiple analog channels. The input channels can be
software configured into three modes: differential, single
ended, or pseudo-differential. Figure 1 shows the three
modes using the 4-channel MUX ADC0844. The eight inputs
of the ADC0848 can also be configured in any of the three
modes. In the differential mode, theADC0844 channel inputs
are grouped in pairs, CH1 with CH2 and CH3 with CH4. The
polarity assignment of each channel in the pair is inter-
changeable. The single-ended mode has CH1–CH4 as-
signed as the positive input with the negative input being the
analog ground (AGND) of the device. Finally, in the
pseudo-differential mode CH1–CH3 are positive inputs ref-
erenced to CH4 which is now a pseudo-ground. This
pseudo-ground input can be set to any potential within the in-
put common-mode range of the converter. The analog signal
conditioning required in transducer-based data acquisition
systems is significantly simplified with this type of input flex-
ibility. One converter package can now handle ground refer-
enced inputs and true differential inputs as well as signals
with some arbitrary reference voltage.
The analog input voltages for each channel can range from
50 mV below ground to 50 mV above V
CC
(typically 5V) with-
out degrading conversion accuracy.
TABLE 1. ADC0844 MUX ADDRESSING
MUX Address
MA2
L
L
L
L
H
H
H
H
H
H
H
X
CS
WR
RD
Channel
#
CH3
MUX
Mode
MA3
X
X
X
X
L
L
L
L
H
H
H
X
MA1
L
L
H
H
L
L
H
H
L
L
H
X
MA0
L
H
L
H
L
H
L
H
L
H
L
X
CH1
+
CH2
+
CH4
AGND
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
L
L
Differential
+
+
+
L
+
Single-Ended
+
+
+
Pseudo-
Differential
L
+
+
L
Previous Channel Configuration
X=don’t care
www.national.com
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