- 您现在的位置：买卖IC网 > PDF目录378279 > ADC0851CIN (NATIONAL SEMICONDUCTOR CORP) 8-Bit Analog Data Acquisition and Monitoring Systems PDF资料下载
参数资料
| 型号： | ADC0851CIN |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | ADC |
| 英文描述： | 8-Bit Analog Data Acquisition and Monitoring Systems |
| 中文描述： | 2-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP16 |
| 封装： | PLASTIC, DIP-16 |
| 文件页数： | 24/36页 |
| 文件大小： | 581K |
| 代理商： | ADC0851CIN |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页当前第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页
3.0 Watchdog Mode
(Continued)
their respective window limits. A logical ‘‘1’’ will be placed in
the appropriate location of the status register for each limit
that is crossed as the device cycles through the remaining
channels. Note that the tag register is updated only once
i.e., when the first limit is exceeded. After the last limit com-
parison is made subsequent to the first limit crossing, the
device will cease any further limit comparisons and will
cause the interrupt pin to go low. Taking CS low causes the
data in the status and tag registers to be transmitted along
with the programmed channel configuration information. In
addition, an extra bit, P, is inserted between the channel
and status information. This bit is updated to a logic ‘‘1’’ in
case of a power interruption.
The format for the output data is as shown below.
Data Output (DO) WordDADC0851
TL/H/11021–46
Data Output (DO) WordDADC0858
TL/H/11021–47
The order in which data is transmitted is as follows
(ADC0851 or ADC0858):
#
Tags (4 bits)DMSB (T3) first
#
Channel configuration (12 bits)DMSB (C11) first
#
Power interrupt (1 bit)
#
Status (4 bits for ADC0851, 16 bits for ADC0858)DMSB
(S3/S15) first
It is important to note that any channel that is disabled will
not cause an interrupt. Furthermore, when operated in the
differential mode, the arithmetic difference of the two volt-
ages will be compared with the lower and upper limits for
the lower numbered channel. For example, with CH0 and
CH1 operating as a differential input pair, the CH0 limits will
apply.
Consider an example where the lower limit of CH1 is
crossed first and while the remaining limits are being
checked, the upper limit of CH0 is crossed. Figure 8 illus-
trates the sequence of events for the ADC0851. During
watchdog operation, CH0’s lower limit stored in the RAM is
compared against the input voltage at CH0. Since no limit
crossing is detected, the upper limit is compared against
CH0 input voltage. Again no limit crossing is detected and
so CH1’s lower limit is next compared against the CH1 input
voltage. This time a limit crossing is detected and a logic
‘‘1’’ is now stored in the MSB (S3) position of the status
register (see Table IV(a)). Also the Tag register is updated
with the corresponding address (0 0 1 0) from Table IV(a).
The device now cycles through the remaining channels
once more. Since no limit crossing is detected for the upper
limit of CH1, a logic ‘‘0’’ is stored for S2 of the status regis-
ter. Similarly a logic ‘‘0’’ is stored for S1 of the status regis-
ter. Finally to complete the cycle, the last limit (upper limit of
CH0) is checked and a limit crossing is detected. Conse-
quently, a logic ‘‘1’’ is stored for S0. Note that the Tag regis-
ter is only updated once when the first limit crossing is de-
tected thus indicating which channel first exceeded its lower
or upper limit.
TL/H/11021–45
(Example: Lower limit of CH1 is crossed first. During cycle through, upper
limit of CH0 is crossed)
FIGURE 8. Example of Limit Crossing
Detection (ADC0851)
Assuming that there is no power interruption and that the
ADC0851 was configured for single ended operation, the
output word for our example would be:
(Example of ADC0851 Data Output. Single ended input.
Lower limit of CH1 fails first. During cycle through, upper
limitDCH0 failure is detected).
0
0
1
0
X
X
X
X
X . . .
0
0 0 1
0
0
1
T3 T2 T1 T0 C11 C10 C9 C8 C7
X
e
Don’t care, whatever bit was initially programmed (ADC0851 only).
The ADC0858 operates similar to the ADC0851 except that
the ADC0858 has a 16-bit status word for the sixteen limits
and sixteen tag addresses (See Table IV(b)). The output
word transmitted to the microprocessor not only contains
information as to how the channels are configured but also
which input crossed which limit. If desired, the microproces-
sor can go through a status bit normalization routine to nor-
malize the status information with the tag number as will be
discussed next.
C1 C0 P S3 S2 S1 S0
3.3 STATUS BIT NORMALIZATION
Figure 9 shows the procedure for normalizing the status in-
formation. Let’s consider the example cited earlier for the
ADC0851. In our example, the lower limit of CH1 was
crossed first and during cycle-through, upper limitDCH0
crossing was detected. The serial status data is thus 1 0 0 1
and the tag data 0 0 1 0 corresponds to tag
Y
2 (see Table
IVa). Since the most significant bit (S3) of the status data is
transmitted first, the data stored in the microprocessor’s
memory is 1 0 0 1. The microprocessor next computes the
tag number from the tag data and rotates the status bits left
‘‘TAG’’ places as in Figure 9. For our example, the status
bits are rotated by shifting left 2 places. The status informa-
tion in the microprocessor’s memory is now normalized i.e.,
U0 corresponds to tag 0, U1 corresponds to tag 1 and so
on. From the example inFigure 9 we can see that the status
register in the microprocessor’s memory shows that tag 2
and tag 1 failed. The ADC0858 uses a 16-bit status word
and operates similar to the ADC0851. An example shown in
Figure 9 for the ADC0858 demonstrates how status bit nor-
malization is carried out.
24
相关PDF资料 |
PDF描述 |
|---|---|
| ADC0851CIV | 8-Bit Analog Data Acquisition and Monitoring Systems |
| ADC0858CIN | 8-Bit Analog Data Acquisition and Monitoring Systems |
| ADC0858CIV | 8-Bit Analog Data Acquisition and Monitoring Systems |
| ADC0881 | 8-Bit 20 MSPS Flash A/D Converter |
| ADC0881CCC | 8-Bit 20 MSPS Flash A/D Converter |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ADC0851CIV | 制造商:NSC 制造商全称:National Semiconductor 功能描述:8-Bit Analog Data Acquisition and Monitoring Systems |
| ADC0851CMJ/883 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Single-Ended Data Acquisition System |
| ADC0852 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:Multiplexed Comparator with 8-Bit Reference Divider |
| ADC0852BCJ/A+ | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Analog Comparator |
| ADC0852BCN | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Analog Comparator |
发布紧急采购，3分钟左右您将得到回复。