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| 型号： | ADCMP573BCPZ-R2 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 5/16页 |
| 文件大小： | 0K |
| 描述： | IC COMPARATOR PECL 3.3-5 16LFCSP |
| 标准包装： | 1 |
| 类型： | 带锁销 |
| 元件数： | 1 |
| 输出类型： | 补充型，PECL |
| 电压 - 电源，单路/双路(±)： | 3.1 V ~ 5.4 V |
| 电压 - 输入偏移（最小值）： | 2mV @ 3.3V |
| 电流 - 输入偏压（最小值）： | 25µA @ 3.3V |
| 电流 - 输出（标准）： | 35mA |
| 电流 - 静态（最大值）： | 80mA |
| CMRR, PSRR（标准）： | 65dB CMRR，74dB PSRR |
| 传输延迟（最大）： | 0.165ns |
| 磁滞： | ±1mV |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 16-VFQFN 裸露焊盘，CSP |
| 安装类型： | 表面贴装 |
| 包装： | 标准包装 |
| 产品目录页面： | 764 (CN2011-ZH PDF) |
| 配用： | EVAL-ADCMP573BCPZ-ND - BOARD EVALUATION ADCMP573BCP |
| 其它名称： | ADCMP573BCPZ-R2DKR |
ADCMP572/ADCMP573
Rev. A | Page 13 of 16
TIMING INFORMATION
Figure 29 illustrates the ADCMP572/ADCMP573 compare and latch timing relationships. Table 4 provides definitions of the terms
shown in the figure.
50%
VN ± VOS
50%
DIFFERENTIAL
INPUT VOLTAGE
LATCH ENABLE
Q OUTPUT
LATCH ENABLE
tH
tPDL
tPDH
tPLOH
tPLOL
tR
tF
VIN
VOD
tS
tPL
04409-003
Figure 29. System Timing Diagram
Table 4. Timing Descriptions
Symbol
Timing
Description
tPDH
Input to output high delay
Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output low-to-high transition.
tPDL
Input to output low delay
Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output high-to-low transition.
tPLOH
Latch enable to output high delay
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output low-to-high transition.
tPLOL
Latch enable to output low delay
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output high-to-low transition.
tH
Minimum hold time
Minimum time after the negative transition of the latch enable signal that the input
signal must remain unchanged to be acquired and held at the outputs.
tPL
Minimum latch enable pulse width
Minimum time that the latch enable signal must be high to acquire an input signal
change.
tS
Minimum setup time
Minimum time before the negative transition of the latch enable signal that an input
signal change must be present to be acquired and held at the outputs.
tR
Output rise time
Amount of time required to transition from a low to a high output as measured at the
20% and 80% points.
tF
Output fall time
Amount of time required to transition from a high to a low output as measured at the
20% and 80% points.
VOD
Voltage overdrive
Difference between the input voltages VA and VB.
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| ADCMP573BCPZ-RL7 | 功能描述:IC COMPARATOR PECL 3.3-5 16LFCSP RoHS:是 类别:集成电路 (IC) >> 线性 - 比较器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 类型:通用 元件数:1 输出类型:CMOS，推挽式，满摆幅，TTL 电压 - 电源，单路/双路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 电压 - 输入偏移（最小值）:5mV @ 5.5V 电流 - 输入偏压（最小值）:1pA @ 5.5V 电流 - 输出（标准）:- 电流 - 静态（最大值）:24µA CMRR, PSRR（标准）:80dB CMRR，80dB PSRR 传输延迟（最大）:450ns 磁滞:±3mV 工作温度:-40°C ~ 85°C 封装/外壳:6-WFBGA，CSPBGA 安装类型:表面贴装 包装:管件 其它名称:Q3554586 |
| ADCMP573BCPZ-WP | 功能描述:IC COMPARATOR PECL 3.3-5 16LFCSP RoHS:是 类别:集成电路 (IC) >> 线性 - 比较器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 类型:通用 元件数:1 输出类型:CMOS，推挽式，满摆幅，TTL 电压 - 电源，单路/双路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 电压 - 输入偏移（最小值）:5mV @ 5.5V 电流 - 输入偏压（最小值）:1pA @ 5.5V 电流 - 输出（标准）:- 电流 - 静态（最大值）:24µA CMRR, PSRR（标准）:80dB CMRR，80dB PSRR 传输延迟（最大）:450ns 磁滞:±3mV 工作温度:-40°C ~ 85°C 封装/外壳:6-WFBGA，CSPBGA 安装类型:表面贴装 包装:管件 其它名称:Q3554586 |
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