参数资料
型号: ADCMP671-1YUJZ-RL7
厂商: Analog Devices Inc
文件页数: 7/16页
文件大小: 0K
描述: IC MONITOR UV/OV LP ADJ 6TSOT
标准包装: 1
类型: 通用
元件数: 1
输出类型: 开路漏极
电压 - 电源,单路/双路(±): 1.7 V ~ 5.5 V
电流 - 输入偏压(最小值): 2.5nA
电流 - 静态(最大值): 11µA
传输延迟(最大): 10µs
磁滞: 9.2mV
工作温度: -40°C ~ 125°C
封装/外壳: SOT-23-6 细型,TSOT-23-6
安装类型: 表面贴装
包装: 标准包装
其它名称: ADCMP671-1YUJZ-RL7DKR
Data Sheet
ADCMP671
Rev. 0 | Page 15 of 16
OUTPUTS
The PWRGD output is used to indicate supply power good for
the rail being monitored. It asserts if the monitored voltage falls
within the UV and OV threshold window. The OV output acts
as a dedicated overvoltage indication output, allows the board
manager to take decisive action to protect the system from
overvoltage faults. Both outputs are open-drain and can be
pulled up to voltages above VDD. These outputs are capable of
sinking current up to 40 mA.
In the multisupply monitoring application, multiple ADCMP671
can be used with their OV pin tied together to generate a single
overvoltage fault alert signal, as shown in
. During power
up and power down, the power management processor of the
board can manage supply sequencing based on PWRGD signals.
In the event of supply overvoltage fault, the processor can react
quickly to the provide necessary circuit protection because of its
dedicated
OV alert. The processor is also able to identify the faulty
supply from combining the information on the PWRGD pins.
This allows the processor to use the N + 1 input pins to
individually monitor N channels of supplies.
2.5V
PWRGD
OV
2.5V GOOD
1.8V GOOD
1.0V GOOD
0.9V GOOD
OV FAULT
BOARD
MANAGER
ADCMP671
1.8V
PWRGD
OV
ADCMP671
1.0V
PWRGD
OV
ADCMP671
0.9V
PWRGD
OV
ADCMP671
10
16
0-
0
35
Figure 35. N Rails Monitoring with N + 1 Processor I/O
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