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参数资料
型号： ADE7156ASTZF8-RL
厂商： Analog Devices Inc
文件页数： 133/152页
文件大小： 0K
描述： IC ENERGY METER 64-LQFP
产品变化通告： Product Discontinuance 27/Oct/2011
标准包装： 1,500
输入阻抗： *
测量误差： *
电压 - 高输入/输出： *
电压 - 低输入/输出： *
电流 - 电源： *
电源电压： *
测量仪表类型： *
工作温度： *
安装类型： 表面贴装
封装/外壳： 64-LQFP
供应商设备封装： 64-LQFP（10x10）
包装： 带卷 (TR)

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
SERIAL PERIPHERAL INTERFACE (SPI)
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 integrate a complete hardware serial peripheral
interface on-chip. The SPI is full duplex so that eight bits of data
are synchronously transmitted and simultaneously received.
This SPI implementation is double buffered, allowing users to
read the last byte of received data while a new byte is shifted in.
The next byte to be transmitted can be loaded while the current
byte is shifted out.
The SPI port can be configured for master or slave operation.
The physical interface to the SPI is via the MISO (P0.5/MISO),
MOSI (P0.4/MOSI/SDATA), SCLK (P0.6/SCLK/T0), and SS
SPI REGISTERS
Table 145. SPI SFR List
(P0.7/SS/T1) pins, while the firmware interface is via the SPI
Configuration SFR 1 (SPIMOD1, Address 0xE8), the SPI
Configuration SFR 2 (SPIMOD2, Address 0xE9), the SPI
interrupt status SFR (SPISTAT, Address 0xEA), the SPI/I 2 C
transmit buffer SFR (SPI2CTx, Address 0x9A), and the SPI/I 2 C
receive buffer SFR (SPI2CRx, Address 0x9B).
Note that the SPI pins are shared with the I 2 C pins. Therefore, the
user can enable only one interface at a time. The SCPS bit in the
configuration SFR (CFG, Address 0xAF) selects which peripheral
is active.
SFR Address
0x9A
0x9B
0xE8
0xE9
0xEA
Mnemonic
SPI2CTx
SPI2CRx
SPIMOD1
SPIMOD2
SPISTAT
R/W
W
R
R/W
R/W
R/W
Length (Bits)
8
8
8
8
8
Default
0
0
0x10
0
0
Description
SPI/I 2 C transmit buffer (see Table 146).
SPI/I 2 C receive buffer (see Table 147).
SPI Configuration SFR 1 (see Table 148).
SPI Configuration SFR 2 (see Table 149).
SPI/I 2 C interrupt status (see Table 150).
Table 146. SPI/I 2 C Transmit Buffer SFR (SPI2CTx, Address 0x9A)
Bit
[7:0]
Mnemonic
SPI2CTx
Default
0
Description
SPI or I 2 C transmit buffer. When the SPI2CTx SFR is written, its content is transferred to the transmit
FIFO input. When a write is requested, the FIFO output is sent on the SPI or I 2 C bus.
Table 147. SPI/I 2 C Receive Buffer SF R (SPI2CRx, Address 0x9B)
Bit
[7:0]
Mnemonic
SPI2CRx
Default
0
Description
SPI or I 2 C receive buffer. When SPI2CRx SFR is read, one byte from the receive FIFO output is
transferred to SPI2CRx SFR. A new data byte from the SPI or I 2 C bus is written to the FIFO input.
Rev. B | Page 133 of 152
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