参数资料
型号: ADE7156ASTZF8
厂商: Analog Devices Inc
文件页数: 101/152页
文件大小: 0K
描述: IC ENERGY METER 64-LQFP
产品变化通告: Product Discontinuance 27/Oct/2011
标准包装: 160
输入阻抗: *
测量误差: *
电压 - 高输入/输出: *
电压 - 低输入/输出: *
电流 - 电源: *
电源电压: *
测量仪表类型: *
工作温度: *
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-LQFP(10x10)
包装: 托盘
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Table 89. LCD Configuration X SFR (LCDCONX, Address 0x9C)
Bit
7
6
Mnemonic
Reserved
EXTRES
Default
0
0
Description
Reserved.
External resistor ladder selection bit.
EXTRES Result
0
1
External resistor ladder is disabled. Charge pump is enabled.
External resistor ladder is enabled. Charge pump is disabled.
[5:0]
BIASLV
0
Bias level selection bits. See Table 90. 1
1
This feature is not available in the ADE7116.
Table 90. LCD Bias Voltage When Contrast Control Is Enabled 1
1/2 Bias
1/3 Bias
[ ]
V REF ×
? BLVL [ 4 : 0 ] ?
BIASLVL[5]
0
1
V A (V)
BLVL 4 : 0
31
V REF × ? 1 + ?
? 31 ?
V B
V B = V A
V B = V A
V C
V C = 2 × V A
V C = 2 × V A
V B
V B = 2 × V A
V B = 2 × V A
V C
V C = 3 × V A
V C = 3 × V A
1
This feature is not available in the ADE7116.
Table 91. LCD Configuration Y SFR (LCDCONY, Address 0xB1)
Bit
7
6
Mnemonic
Reserved
INV_LVL
Default
0
0
Description
This bit should be kept cleared for proper operation.
Frame inversion mode enable bit. If this bit is set, frames are inverted every other frame. If this bit is
cleared, frames are not inverted.
[5:2]
1
Reserved
UPDATEOVER
0000
0
These bits should be kept cleared to 0 for proper operation.
Update finished flag bit. This bit is updated by the LCD driver. When set, this bit indicates that the
LCD memory has been updated and a new frame has begun.
0
REFRESH
0
Refresh LCD data memory bit. This bit should be set by the user. When set, the LCD driver does not
use the data in the LCD data registers to update the display. The LCD data registers can be updated
by the 8052. When cleared, the LCD driver uses the data in the LCD data registers to update display
at the next frame.
Table 92. LCD Clock SFR (LCDCLK, Address 0x96)
Bit
[7:6]
Mnemonic
BLKMOD
Default
0
Description
Blink mode clock source configuration bits.
BLKMOD Result
00
01
10
11
The blink rate is controlled by software; the display is off.
The blink rate is controlled by software; the display is on.
The blink rate is 2 Hz.
The blink rate is set by BLKFREQ.
[5:4]
BLKFREQ
0
Blink rate configuration bits. These bits control the LCD blink rate if the BLKMOD bits = 11.
BLKFREQ Result (Blink Rate)
00 1 Hz
01 1/2 Hz
10 1/3 Hz
11 1/4 Hz
[3:0]
FD
0
LCD frame rate selection bits. See Table 93 and Table 94.
Rev. B | Page 101 of 152
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