参数资料
型号: ADE7753ARSZRL
厂商: Analog Devices Inc
文件页数: 6/60页
文件大小: 0K
描述: IC ENERGY METERING 1PHASE 20SSOP
标准包装: 1,500
输入阻抗: 390 千欧
测量误差: 0.1%
电压 - 高输入/输出: 2.4V
电压 - 低输入/输出: 0.8V
电流 - 电源: 3mA
电源电压: 4.75 V ~ 5.25 V
测量仪表类型: 单相
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 20-SSOP(0.209",5.30mm 宽)
供应商设备封装: 20-SSOP
包装: 带卷 (TR)
配用: EVAL-ADE7753ZEB-ND - BOARD EVALUATION AD7753

ADE7753
TIMING CHARACTERISTICS
AV DD = DV DD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 3.579545 MHz XTAL, T MIN to T MAX = ?40°C to +85°C.
Sample tested during initial release and after any redesign or process change that could affect this parameter. All input signals are specified with
tr = tf = 5 ns (10% to 90%) and timed from a voltage level of 1.6 V. See Figure 3, Figure 4, and the ADE7753 Serial Interface section.
Table 2.
Parameter
Spec
Unit
Test Conditions/Comments
Write Timing
t 1
t 2
t 3
t 4
t 5
t 6
t 7
t 8
50
50
50
10
5
4
50
100
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
μs (min)
ns (min)
ns (min)
CS falling edge to first SCLK falling edge.
SCLK logic high pulse width.
SCLK logic low pulse width.
Valid data setup time before falling edge of SCLK.
Data hold time after SCLK falling edge.
Minimum time between the end of data byte transfers.
Minimum time between byte transfers during a serial write.
CS hold time after SCLK falling edge.
Read Timing
t 9 1
4
μs (min)
Minimum time between read command (i.e., a write to communication
register) and data read.
t 10
t 11
50
30
ns (min)
ns (min)
Minimum time between data byte transfers during a multibyte read.
Data access time after SCLK rising edge following a write to the
communications register.
t 13 3
100
10
100
10
ns (max)
ns (min)
ns (max)
ns (min)
Bus relinquish time after falling edge of SCLK.
Bus relinquish time after rising edge of CS.
1
2
3
Minimum time between read command and data read for all registers except waveform register, which is t 9 = 500 ns min.
Measured with the load circuit in Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V.
Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish time of
the part and is independent of the bus loading.
t 8
CS
SCLK
t 1
t 3
t 7
t 7
t 6
t 2
t 4
t 5
DIN
1
0
A5
A4
A3
A2
A1
A0
DB7
DB0
DB7
DB0
COMMAND BYTE
MOST SIGNIFICANT BYTE
LEAST SIGNIFICANT BYTE
02875-0-081
Figure 3. Serial Write Timing
CS
t 1
t 13
SCLK
t 9
t 10
DIN
0
0
A5
A4
A3
A2
A1
A0
t 11
t 11
t 12
DOUT
DB7
DB0
DB7
DB0
COMMAND BYTE
MOST SIGNIFICANT BYTE
LEAST SIGNIFICANT BYTE
02875-0-083
Figure 4. Serial Read Timing
Rev. C | Page 6 of 60
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