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| 型号： | ADE7768ARZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 4/20页 |
| 文件大小： | 0K |
| 描述： | IC ENERGY METERING 1PHASE 16SOIC |
| 标准包装： | 2,500 |
| 输入阻抗： | 320 千欧 |
| 测量误差： | 0.1% |
| 电压 - 高输入/输出： | 2.4V |
| 电压 - 低输入/输出： | 0.8V |
| 电流 - 电源： | 5mA |
| 电源电压： | 4.75 V ~ 5.25 V |
| 测量仪表类型： | 单相 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 带卷 (TR) |
ADE7768
Parameter
POWER SUPPLY
V DD
I DD
Value
4.75
5.25
5
Unit
V min
V max
mA max
Test Conditions/Comments
For specified performance
5 V – 5%
5 V + 5%
Typically 4 mA
1
2
3
See the Terminology section for an explanation of specifications.
See the figures in the Typical Performance Characteristics section.
Sample tested during initial release and after any redesign or process change that may affect this parameter.
TIMING CHARACTERISTICS
V DD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, RCLKIN = 6.2 kΩ, 0.5% ± 50 ppm/°C, T MIN to T MAX = –40°C to +85°C,
unless otherwise noted. Sample tested during initial release and after any redesign or process change that may affect this parameter.
See Figure 2.
Table 2.
Parameter
Specifications
Unit
Test Conditions/Comments
t 1
1
120
ms
F1 and F2 pulse width (logic low)
t 2
t 3
t 41, 2
t 5
t 6
See Table 6
1/2 t 2
90
See Table 7
2
sec
sec
ms
sec
μs
Output pulse period. See the Transfer Function section.
Time between the F1 and F2 falling edges.
CF pulse width (logic high).
CF pulse period. See the Transfer Function section.
Minimum time between the F1 and F2 pulses.
1
2
The pulse widths of F1, F2, and CF are not fixed for higher output frequencies. See the Frequency Outputs section.
The CF pulse is always 35 μs in high frequency mode. See the Frequency Outputs section and Table 7.
t 1
F1
t 6
t 2
F2
t 4
t 3
t 5
CF
Figure 2. Timing Diagram for Frequency Outputs
Rev. A | Page 4 of 20
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