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| 型号： | ADE7769ARZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 12/20页 |
| 文件大小： | 0K |
| 描述： | IC ENERGY METERING 1PHASE 16SOIC |
| 标准包装： | 48 |
| 输入阻抗： | 320 千欧 |
| 测量误差： | 0.1% |
| 电压 - 高输入/输出： | 2.4V |
| 电压 - 低输入/输出： | 0.8V |
| 电流 - 电源： | 5mA |
| 电源电压： | 4.75 V ~ 5.25 V |
| 测量仪表类型： | 单相 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 管件 |
ADE7769
R A *
R B
V2P
Equation 6 shows how the power calculation is affected by the
R F
C F
± 165mV V2N
dc offsets in the current and voltage channels.
R F
C F
{ V cos ( ωt ) + V OS } × { I cos ( ωt ) + I OS }
(6)
NEUTRAL PHASE
*R A >> R B + R F
=
V × I
2
+ V OS × I OS + V OS × I cos ( ωt ) + I OS × V cos ( ωt )
Figure 20. Typical Connections for Channel V2
POWER SUPPLY MONITOR
+
V × I
2
× cos ( 2 ωt )
The ADE7769 contains an on-chip power supply monitor. The
power supply (V DD ) is continuously monitored by the ADE7769.
DC COMPONENT (INCLUDING ERROR TERM)
IS EXTRACTED BY THE LPF FOR REAL
If the supply is less than 4 V, the ADE7769 becomes inactive.
This is useful to ensure proper device operation at power-up
and power-down. The power supply monitor has built-in
hysteresis and filtering, which provide a high degree of
immunity to false triggering from noisy supplies.
In Figure 21, the trigger level is nominally set at 4 V. The toler-
ance on this trigger level is within ±5%. The power supply and
V OS × I OS
V × I
2
0
POWER CALCULATION
I OS × V
V OS × I
FREQUENCY (RAD/s)
decoupling for the part should be such that the ripple at V DD
does not exceed 5 V ± 5%, as specified for normal operation.
V DD
5V
4V
0V
Figure 22. Effect of Channel Offset on the Real Power Calculation
The HPF in Channel V1 has an associated phase response that
is compensated for on chip. Figure 23 and Figure 24 show the
phase error between channels with the compensation network
activated. The ADE7769 is phase compensated up to 1 kHz as
shown. This ensures correct active harmonic power calculation
even at low power factors.
0.30
TIME
0.25
INTERNAL
ACTIVATION
INACTIVE
ACTIVE
INACTIVE
0.20
0.15
Figure 21. On-Chip Power Supply Monitor
HPF and Offset Effects
Figure 22 shows the effect of offsets on the real power calcula-
tion. As can be seen, offsets on Channel V1 and Channel V2
contribute a dc component after multiplication. Because this dc
0.10
0.05
0
–0.05
component is extracted by the LPF and used to generate the real
power information, the offsets contribute a constant error to the
–0.10
0
100
200
300
400 500 600
FREQUENCY (Hz)
700
800
900 1000
real power calculation. This problem is easily avoided by the
built-in HPF in Channel V1. By removing the offsets from at
least one channel, no error component can be generated at dc
by the multiplication. Error terms at the line frequency ( ω ) are
removed by the LPF and the digital-to-frequency conversion
(see the Digital-to-Frequency Conversion section).
Rev. A | Page 12 of 20
Figure 23. Phase Error Between Channels (0 Hz to 1 kHz)
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|---|---|
| ADE7769ARZ-RL | 功能描述:IC ENERGY METERING 1PHASE 16SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - 能量测量 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:* |
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| ADE7816ACPZ-RL | 功能描述:IC ENERGY METERING 40LFCSP RoHS:是 类别:集成电路 (IC) >> PMIC - 能量测量 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:* |
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