参数资料
型号: ADEL2020ARZ-20-RL
厂商: Analog Devices Inc
文件页数: 11/12页
文件大小: 0K
描述: IC OPAMP CF LN LP 60MA 20SOIC
标准包装: 2,500
放大器类型: 电流反馈
电路数: 1
转换速率: 500 V/µs
-3db带宽: 90MHz
电流 - 输入偏压: 1µA
电压 - 输入偏移: 1500µV
电流 - 电源: 6.8mA
电流 - 输出 / 通道: 60mA
电压 - 电源,单路/双路(±): 6 V ~ 36 V,±3 V ~ 18 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 20-SOIC(0.295",7.50mm 宽)
供应商设备封装: 20-SOIC W
包装: 带卷 (TR)
REV. A
–8–
ADEL2020
GENERAL DESIGN CONSIDERATIONS
The ADEL2020 is a current feedback amplifier optimized for
use in high performance video and data acquisition systems.
Since it uses a current feedback architecture, its closed-loop
bandwidth depends on the value of the feedback resistor. The
–3 dB bandwidth is also somewhat dependent on the power
supply voltage. Lowering the supplies increases the values of
internal capacitances, reducing the bandwidth. To compen-
sate for this, smaller values of feedback resistors are used at
lower supply voltages.
POWER SUPPLY BYPASSING
Adequate power supply bypassing can be critical when optimiz-
ing the performance of a high frequency circuit. Inductance in
the power supply leads can contribute to resonant circuits that
produce peaking in the amplifier’s response. In addition, if large
current transients must be delivered to the load, then bypass
capacitors (typically greater than 1
F) will be required to
provide the best settling time and lowest distortion. Although
the recommended 0.1
F power supply bypass capacitors will
be sufficient in most applications, more elaborate bypassing
(such as using two paralleled capacitors) may be required in
some cases.
CAPACITIVE LOADS
When used with the appropriate feedback resistor, the ADEL2020
can drive capacitive loads exceeding 1000 pF directly without
oscillation. Another method of compensating for large load
capacitance is to insert a resistor in series with the loop output.
In most cases, less than 50
is all that is needed to achieve an
extremely flat gain response.
OFFSET NULLING
A 10 k
pot connected between Pins 1 and 5, with its wiper con-
nected to V+, can be used to trim out the inverting input current
(with about
±20 A of range). For closed-loop gains above about
5, this may not be sufficient to trim the output offset voltage to
zero. Tie the pot’s wiper to ground through a large value resistor
(50 k
for ±5 V supplies, 150 k for ±15 V supplies) to trim the
output to zero at high closed-loop gains.
OPERATION AS A VIDEO LINE DRIVER
The ADEL2020 is designed to offer outstanding performance at
closed-loop gains of 1 or greater. At a gain of 2, the ADEL2020
makes an excellent video line driver. The low differential gain
and phase errors and wide –0.1 dB bandwidth are nearly inde-
pendent of supply voltage and load. For applications requiring
widest 0.1 dB bandwidth, it is recommended to use 715
feed-
back and gain resistors. This will result in about 0.05 dB of
peaking and a –0.1 dB bandwidth of 30 MHz on
±15 V supplies.
DISABLE MODE
By pulling the voltage on Pin 8 to common (0 V), the ADEL2020
can be put into a disabled state. In this condition, the supply
current drops to less than 2.8 mA, the output becomes a high
impedance, and there is a high level of isolation from input to
output. In the case of a line driver, for example, the output
impedance will be about the same as that for a 1.5 k
resistor
(the feedback plus gain resistors) in parallel with a 13 pF capacitor
(due to the output), and the input to output isolation will be
better than 50 dB at 10 MHz.
Leaving the disable pin disconnected (floating) will leave the
part in the enabled state.
In cases where the amplifier is driving a high impedance load,
the input to output isolation will decrease significantly if the
input signal is greater than about 1.2 V p–p. The isolation can
be restored to the 50 dB level by adding a dummy load (say 150
)
at the amplifier output. This will attenuate the feedthrough
signal. (This is not an issue for multiplexer applications where the
outputs of multiple ADEL2020s are tied together as long as at
least one channel is in the ON state.) The input impedance of
the disable pin is about 35 k
in parallel with a few pF. When
grounded, about 50
A flows out of the disable pin for ±5 V supplies.
Break-before-make operation is guaranteed by design. If driven
by standard CMOS logic, the disable time (until the output is
high impedance) is about 100 ns and the enable time (to low
impedance output) is about 160 ns. Since it has an internal pull-
up resistor of about 35 k
, the ADEL2020 can be used with
open drain logic as well. In that case, the enable time increases
to about 1
s.
If there is a nonzero voltage present on the amplifier’s output
at the time it is switched to the disabled state, some additional
decay time will be required for the output voltage to relax to
zero. The total time for the output to go to zero will normally
be about 250 ns; it is somewhat dependent on the load impedance.
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