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参数资料
| 型号： | ADF4106BRUZ-R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 11/24页 |
| 文件大小： | 0K |
| 描述： | IC PLL FREQ SYNTHESIZER 16TSSOP |
| 标准包装： | 1,000 |
| 类型： | 时钟/频率合成器，RF |
| PLL： | 是 |
| 输入： | CMOS，TTL |
| 输出： | 时钟 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:1 |
| 差分 - 输入:输出： | 是/无 |
| 频率 - 最大： | 6GHz |
| 除法器/乘法器： | 无/无 |
| 电源电压： | 2.7 V ~ 3.3 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-TSSOP |
| 包装： | 带卷 (TR) |
| 配用： | EVAL-ADF4106EBZ1-ND - BOARD EVAL FOR ADF4106 |
Data Sheet
ADF4106
Rev. E | Page 19 of 24
APPLICATIONS
LOCAL OSCILLATOR FOR LMDS BASE STATION
TRANSMITTER
Figure 22 shows the ADF4106 being used with a VCO to
produce the LO for an LMDS base station.
The reference input signal is applied to the circuit at FREFIN
and, in this case, is terminated in 50 . A typical base station
system would have either a TCXO or an OCXO driving the
reference input without any 50 termination.
To achieve a channel spacing of 1 MHz at the output, the
10 MHz reference input must be divided by 10, using the
on-chip reference divider of the ADF4106.
The charge pump output of the ADF4106 (Pin 2) drives the
loop filter. In calculating the loop filter component values, a
number of items need to be considered. In this example, the
loop filter was designed so that the overall phase margin for
the system would be 45°.
Other PLL system specifications include:
KD = 2.5 mA
KV = 80 MHz/V
Loop Bandwidth = 50 kHz
FPFD = 1 MHz
N = 5800
Extra Reference Spur Attenuation = 10 dB
These specifications are needed and used to derive the loop
filter component values shown in Figure 22.
The circuit in Figure 22 shows a typical phase noise
performance of 83.5 dBc/Hz at 1 kHz offset from the carrier.
Spurs are better than 62 dBc.
The loop filter output drives the VCO, which in turn is fed
back to the RF input of the PLL synthesizer and also drives the
RF output terminal. A T-circuit configuration provides 50
matching between the VCO output, the RF output, and the RFIN
terminal of the synthesizer.
In a PLL system, it is important to know when the system
is in lock. In Figure 22, this is accomplished by using the
MUXOUT signal from the synthesizer. The MUXOUT pin
can be programmed to monitor various internal signals in the
synthesizer. One of these is the LD or lock-detect signal.
ADF4106
CE
CLK
DATA
LE
1000pF
REFIN
100pF
CP
MUXOUT
CPGND
AGND
DGND
100pF
1.5nF
20pF
100pF
51
6.2k
4.3k
100pF
18
NOTE
DECOUPLING CAPACITORS (0.1
F/10pF) ON AV
DD, DVDD, AND
VP OF THE ADF4106 AND ON VCC OF THE V956ME03 HAVE
BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.
SPI
-COMPATIBLE
SERIAL
BUS
RSET
RFINA
RFINB
AVDD DVDD VP
FREFIN
VDD
VP
LOCK
DETECT
VCC
V956ME03
1, 3, 4, 5, 7, 8,
9, 11, 12, 13
18
18
100pF
RFOUT
5.1k
7
15
16
8
2
14
6
5
1
9
4
3
14
2
10
51
02720-027
Figure 22. Local Oscillator for LMDS Base Station
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