参数资料
| 型号： | ADF4108BCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 15/20页 |
| 文件大小： | 0K |
| 描述： | IC PLL FREQUENCY SYNTH 20-LFCSP |
| 标准包装： | 1 |
| 类型： | 时钟/频率合成器，RF |
| PLL： | 是 |
| 输入： | CMOS，TTL |
| 输出： | 时钟 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:1 |
| 差分 - 输入:输出： | 是/无 |
| 频率 - 最大： | 8GHz |
| 除法器/乘法器： | 无/无 |
| 电源电压： | 3.2 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 20-LFCSP-VQ |
| 包装： | 托盘 |
| 产品目录页面： | 551 (CN2011-ZH PDF) |
ADF4108
Data Sheet
Rev. E | Page 4 of 20
Parameter
B Version1
B Chips2
(Typ)
Unit
Test Conditions/Comments
NOISE CHARACTERISTICS
Normalized Phase Noise Floor
(PNSYNTH)9
223
dBc/Hz typ
PLL loop B/W = 500 kHz, measured at 100 kHz offset
122
dBc/Hz typ
10 kHz offset; normalized to 1 GHz
Phase Noise Performance11
@ VCO output
7900 MHz Output12
81
dBc/Hz typ
@ 1 kHz offset and 1 MHz PFD frequency
Spurious Signals
7900 MHz Output12
82
dBc typ
@ 1 MHz offset and 1 MHz PFD frequency
1
Operating temperature range (B version) is 40°C to +85°C.
2
The B chip specifications are given as typical values.
3
This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that
is less than this value.
4
AVDD = DVDD = 3.3 V.
5
AC coupling ensures AVDD/2 bias.
6
Guaranteed by design. Sample tested to ensure compliance.
7
TA = 25°C; AVDD = DVDD = 3.3 V; P = 32; RFIN = 8 GHz, fPFD = 200 kHz, REFIN = 10 MHz.
8
TA = 25°C; AVDD = DVDD = 3.3 V; R = 16,383; A = 63; B = 891; P = 32; RFIN = 7.0 GHz.
9
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider
value) and 10 log FPFD. PNSYNTH = PNTOT 10 log FPFD 20 log N.
10
The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, fRF,
and at a frequency offset, f, is given by PN = PN1_f + 10 log(10 kHz/f) + 20 log(fRF/1 GHz). All phase noise measurements were performed with the EV-ADF4108EBZ1 and
the Agilent E5500 phase noise system. Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.
11
The phase noise is measured with the EV-ADF4108EB1Z evaluation board, with the ZComm CRO8000Z VCO. The spectrum analyzer provides the REFIN for the
synthesizer (fREFOUT = 10 MHz @ 0 dBm).
12
fREFIN = 10 MHz; fPFD = 1 MHz; fRF = 7900 MHz; N = 7900; loop B/W = 30 kHz, VCO = ZComm CRO8000Z.
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相关代理商/技术参数 |
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|---|---|
| ADF4108BCPZ-RL | 功能描述:IC PLL FREQUENCY SYNTH 20-LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:1,000 系列:Precision Edge® 类型:时钟/频率合成器 PLL:无 输入:CML，PECL 输出:CML 电路数:1 比率 - 输入:输出:2:1 差分 - 输入:输出:是/是 频率 - 最大:10.7GHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-VFQFN 裸露焊盘，16-MLF? 供应商设备封装:16-MLF?（3x3） 包装:带卷 (TR) 其它名称:SY58052UMGTRSY58052UMGTR-ND |
| ADF4108BCPZ-RL7 | 功能描述:IC PLL FREQUENCY SYNTH 20-LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:1,000 系列:Precision Edge® 类型:时钟/频率合成器 PLL:无 输入:CML，PECL 输出:CML 电路数:1 比率 - 输入:输出:2:1 差分 - 输入:输出:是/是 频率 - 最大:10.7GHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-VFQFN 裸露焊盘，16-MLF? 供应商设备封装:16-MLF?（3x3） 包装:带卷 (TR) 其它名称:SY58052UMGTRSY58052UMGTR-ND |
| ADF4108BRUZ | 制造商:Analog Devices 功能描述:PLL FREQ SYNTHESIZER SGL UP TO 325MHZ 16TSSOP - Rail/Tube |
| ADF4108BRUZ-RL | 制造商:AD 制造商全称:Analog Devices 功能描述:PLL Frequency Synthesizer |
| ADF4108BRUZ-RL7 | 制造商:AD 制造商全称:Analog Devices 功能描述:PLL Frequency Synthesizer |
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