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| 型号： | ADF4151BCPZ-RL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 26/28页 |
| 文件大小： | 0K |
| 描述： | IC FRACTION-N FREQ SYNTH 32LFCSP |
| 标准包装： | 1,500 |
| 类型： | * |
| PLL： | 是 |
| 输入： | CMOS，TTL |
| 输出： | 时钟 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:1 |
| 差分 - 输入:输出： | 是/无 |
| 频率 - 最大： | 3.5GHz |
| 除法器/乘法器： | 是/是 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-WQ（5x5） |
| 包装： | 带卷 (TR) |
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Data Sheet
ADF4151
Rev. B | Page 7 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
CLK
2
DATA
3
LE
4
CE
5
SW
6
7
24
23
NC
22
21
20
19
18
17
8
S
DV
DD
ADF4151
TOP VIEW
(Not to Scale)
9
A
G
ND
10
11
RE
F
IN
12
D
G
ND
13
DV
DD
14
15
16
32
31
30
29
28
SD
G
ND
27
26
25
PIN 1
INDICATOR
VP
CPOUT
CPGND
M
UX
O
UT
RSET
NC
RF
IN
+
RF
IN
NC
D
G
ND
LD
A
G
ND
AGND
NC
AVDD2
AV
DD
2
AV
DD
1
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE LFCSP HAS AN EXPOSED PADDLE THAT MUST
BE CONNECTED TO GND.
10265-
003
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
CLK
Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high
impedance CMOS input.
2
DATA
Serial Data Input. The serial data is loaded, MSB first, with the three LSBs as the control bits. This input is a high
impedance CMOS input.
3
LE
Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into the register
that is selected by the three LSBs.
4
CE
Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state
mode. Taking the pin high powers up the device depending on the status of the power-down bits.
5
SW
Fast Lock Switch. Make a connection to this pin from the loop filter when using the fast lock mode.
6
VP
Charge Pump Power Supply. This pin should be greater than or equal to AVDD. In systems where AVDDx is 3 V, it
can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5.5 V.
7
CPOUT
Charge Pump Output. When enabled, this provides ±ICP to the external loop filter. The output of the loop filter
is connected to VTUNE to drive the external VCO.
8
CPGND
Charge Pump Ground. This is the ground return pin for CPOUT.
9, 11, 18,
21
AGND
Analog Ground. This is a ground return pin for AVDD1 and AVDD2.
10
AVDD1
Analog Power Supply. This pin ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane
are to be placed as close as possible to this pin. AVDD must have the same value as DVDD.
12, 13, 19,
20, 23, 24
NC
No connect. Do not connect to this pin.
14
RFIN+
Input to the RF Input. This small signal input is ac-coupled to the external VCO.
15
RFIN
Complementary Input to the RF Input. This pin must be decoupled to the ground plane with a small bypass
capacitor, typically 100 pF.
16, 17
AVDD2
Analog Power Supply. This pin ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane
are to be placed as close as possible to this pin. AVDDx must have the same value as DVDD.
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