参数资料
型号: ADG3241BKSZ-500RL7
厂商: Analog Devices Inc
文件页数: 2/16页
文件大小: 0K
描述: IC SW BUS 2.5-3.3V 1BIT SC70-6
标准包装: 1
类型: 总线开关
电路: 1 x 1:1
独立电路: 1
电压电源: 单电源
电源电压: 2.5V, 3.3V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 6-TSSOP,SC-88,SOT-363
供应商设备封装: SC-70-6
包装: 标准包装
其它名称: ADG3241BKSZ-500RL7DKR
ADG3241
Rev. B | Page 10 of 16
TERMINOLOGY
VCC
Positive power supply voltage.
GND
Ground (0 V) reference.
VINH
Minimum input voltage for Logic 1.
VINL
Maximum input voltage for Logic 0.
II
Input leakage current at the control inputs.
IOZ
Off state leakage current. It is the maximum leakage current at
the switch pin in the off state.
IOL
On state leakage current. It is the maximum leakage current at
the switch pin in the on state.
VP
Maximum pass voltage. The maximum pass voltage relates to
the clamped output voltage of an NMOS device when the
switch input voltage is equal to the supply voltage.
RON
Ohmic resistance offered by a switch in the on state. It is
measured at a given voltage by forcing a specified amount of
current through the switch.
CX OFF
Off switch capacitance.
CX ON
On switch capacitance.
CIN
Control input capacitance. This consists of BE and SEL.
ICC
Quiescent power supply current. This current represents the
leakage current between the VCC and ground pins. It is
measured when all control inputs are at a logic high or low level
and the switches are off.
ΔICC
Extra power supply current component for the BE control input
when the input is not driven at the supplies.
tPLH, tPHL
Data propagation delay through the switch in the on state.
Propagation delay is related to the RC time constant RON × CL,
where CL is the load capacitance.
tPZH, tPZL
Bus enable times. These are the times taken to cross the VT
voltage at the switch output when the switch turns on in
response to the control signal, BE.
tPHZ, tPLZ
Bus disable times. These are the times taken to place the switch
in the high impedance off state in response to the control signal.
It is measured as the time taken for the output voltage to change
by VΔ from the original quiescent level, with reference to the
logic level transition at the control input. Refer to Figure 26 for
enable and disable times.
Max Data Rate
Maximum rate at which data can be passed through the switch.
Channel Jitter
Peak-to-peak value of the sum of the deterministic and random
jitter of the switch channel.
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