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参数资料
| 型号： | ADG3304BRUZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/20页 |
| 文件大小： | 0K |
| 描述： | IC XLATR BIDIR V-LVL 4CH 14TSSOP |
| 标准包装： | 1,000 |
| 逻辑功能： | 变换器，双向 |
| 位数： | 4 |
| 输入类型： | 逻辑 |
| 输出类型： | 逻辑 |
| 数据速率： | 50Mbps |
| 通道数： | 4 |
| 输出/通道数目： | 1 |
| 差分 - 输入:输出： | 无/无 |
| 传输延迟（最大）： | 6ns |
| 电源电压： | 1.15 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 14-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 14-TSSOP |
| 包装： | 带卷 (TR) |
| 其它名称： | ADG3304BRUZ-REEL7-ND ADG3304BRUZ-REEL7TR |
ADG3304
Data Sheet
Rev. D | Page 16 of 20
THEORY OF OPERATION
The ADG3304 level translator allows the level shifting
necessary for data transfer in a system where multiple supply
voltages are used. The device requires two supplies, VCCA and
VCCY (VCCA ≤ VCCY). These supplies set the logic levels on each
side of the device. When driving the A pins, the device translates
the VCCA-compatible logic levels to VCCY-compatible logic levels
available at the Y pins. Similarly, because the device is capable of
bidirectional translation, when driving the Y pins, the VCCY-
compatible logic levels are translated to VCCA-compatible logic
levels available at the A pins. When EN = 0, Pin A1 to Pin A4
and Pin Y1 to Pin Y4 are three-stated. When EN is driven high,
the ADG3304 goes into normal operation mode and performs
level translation.
LEVEL TRANSLATOR ARCHITECTURE
The ADG3304 consists of four bidirectional channels. Each
channel can translate logic levels in either the A→Y or the Y→A
direction. It uses a one-shot accelerator architecture, which
ensures excellent switching characteristics. Figure 39 shows a
simplified block diagram of a bidirectional channel.
ONE-SHOT GENERATOR
6k
6k
Y
VCCA
VCCY
T2
T1
T3
T4
A
04860-053
P
N
U1
U2
U4
U3
Figure 39. Simplified Block Diagram of an ADG3304 Channel
The logic level translation in the A→Y direction is performed
using a level translator (U1) and an inverter (U2), while the
translation in the Y→A direction is performed using Inverter U3
and Inverter U4. The one-shot generator detects a rising or
falling edge present on either the A side or the Y side of the
channel. It sends a short pulse that turns on the PMOS
transistors (T1 to T2) for a rising edge, or the NMOS transistors
(T3 to T4) for a falling edge. This charges/discharges the
capacitive load faster, which results in faster rise and fall times.
The inputs of the unused channels (A or Y) should be tied to
their corresponding VCC rail (VCCA or VCCY) or to GND.
INPUT DRIVING REQUIREMENTS
To ensure correct operation of the ADG3304, the circuit that
drives the input of the ADG3304 channels should have an
output impedance of less than or equal to 150 and a
minimum peak current driving capability of 36 mA.
OUTPUT LOAD REQUIREMENTS
The ADG3304 level translator is designed to drive CMOS-
compatible loads. If current-driving capability is required, it is
recommended to use buffers between the ADG3304 outputs
and the load.
ENABLE OPERATION
The ADG3304 provides three-state operation at the A and Y
I/O pins by using the enable pin (EN), as shown in Table 5.
Table 5. Truth Table
EN
Y I/O Pins
A I/O Pins
0
Hi-Z1
1
Normal operation2
Normal operation2
1
High impedance state.
2
In normal operation, the ADG3304 performs level translation.
While EN = 0, the ADG3304 enters into three-state mode. In this
mode, the current consumption from both the VCCA and VCCY
supplies is reduced, allowing the user to save power, which is
critical, especially on battery-operated systems. The EN input pin
can be driven with either VCCA-compatible or VCCY-compatible
logic levels.
POWER SUPPLIES
For proper operation of the ADG3304, the voltage applied to
the VCCA must be less than or equal to the voltage applied to VCCY.
To meet this condition, the recommended power-up sequence
is VCCY first and then VCCA. The ADG3304 operates properly
only after both supply voltages reach their nominal values. It is
not recommended to use the part in a system where, during
power-up, VCCA can be greater than VCCY due to a significant
increase in the current taken from the VCCA supply. For
optimum performance, the VCCA pin and VCCY pin should be
decoupled to GND as close as possible to the device.
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| ADG3304SRU-EP-RL7 | 功能描述:转换 - 电压电平 1.2 V - 5.5 V 4-channel BI-DIR TRANS IC RoHS:否 制造商:Micrel 类型:CML/LVDS/LVPECL to LVCMOS/LVTTL 传播延迟时间:1.9 ns 电源电流:14 mA 电源电压-最大:3.6 V 电源电压-最小:3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:MLF-8 |
| ADG3304SRUZ-EP-RL7 | 功能描述:IC XLATR BIDIR 1.15-5.5V 14TSSOP 制造商:analog devices inc. 系列:- 零件状态:在售 转换器类型:电压电平 通道类型:双向 电路数:1 每个电路的通道数:4 电压 - VCCA:1.15V ~ 5.5V 电压?- VCCB:1.65V ~ 5.5V 输入信号:- 输出信号:- 输出类型:三态，非反相 数据速率:50Mbps 工作温度:-55°C ~ 125°C（TA） 特性:- 安装类型:表面贴装 封装/外壳:14-TSSOP（0.173"，4.40mm 宽） 供应商器件封装:14-TSSOP 标准包装:1,000 |
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