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| 型号： | ADG433BRZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 6/8页 |
| 文件大小： | 0K |
| 描述： | IC SWITCH QUAD SPST 16SOIC |
| 产品培训模块： | iCMOS™ Switches and Multiplexers for Data Acquisition Switch Fundamentals |
| 标准包装： | 48 |
| 系列： | LC²MOS |
| 功能： | 开关 |
| 电路： | 4 x SPST - NC/NO |
| 导通状态电阻： | 42 欧姆 |
| 电压电源： | 单/双电源 |
| 电压 - 电源，单路/双路(±)： | 12V，±15V |
| 电流 - 电源： | 100pA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 管件 |
| 产品目录页面： | 800 (CN2011-ZH PDF) |
ADG431/ADG432/ADG433
REV. C
–6–
FREQUENCY – Hz
120
100
40
100
10M
1k
OFF
ISOLATION
–
dB
10k
100k
1M
80
60
VDD = +15V
VSS = –15V
VL = +5V
TPC 7. Off Isolation vs. Frequency
FREQUENCY – Hz
110
100
60
100
10M
1k
CROSSTALK
–
dB
10k
100k
1M
90
80
70
VDD = +15V
VSS = –15V
VL = +5V
TPC 8. Crosstalk vs. Frequency
TRENCH ISOLATION
In the ADG431A, ADG432A and ADG433A, an insulating
oxide layer (trench) is placed between the NMOS and PMOS
transistors of each CMOS switch. Parasitic junctions, which
occur between the transistors in junction isolated switches, are
eliminated, the result being a completely latch-up proof switch.
In junction isolation, the N and P wells of the PMOS and NMOS
transistors from a diode that is reverse-biased under normal
operation. However, during overvoltage conditions, this diode
becomes forward biased. A silicon-controlled rectifier (SCR)
type circuit is formed by the two transistors causing a significant
amplification of the current which, in turn, leads to latch up.
With trench isolation, this diode is removed, the result being a
latch-up proof switch.
BURIED OXIDE LAYER
SUBSTRATE (BACKGATE)
T
R
E
N
C
H
T
R
E
N
C
H
T
R
E
N
C
H
P+
P-CHANNEL
N+
N-CHANNEL
P–
N–
VG
VD
VS
VG
VD
VS
Figure 1. Trench Isolation
APPLICATION
Figure 2 illustrates a precise, fast sample-and-hold circuit.
An AD845 is used as the input buffer while the output opera-
tional amplifier is an AD711. During the track mode, SW1 is
closed and the output VOUT follows the input signal VIN. In
the hold mode, SW1 is opened and the signal is held by the
hold capacitor CH.
Due to switch and capacitor leakage, the voltage on the hold
capacitor will decrease with time. The ADG431/ADG432/
ADG433 minimizes this droop due to its low leakage specifica-
tions. The droop rate is further minimized by the use of a
polystyrene hold capacitor. The droop rate for the circuit
shown is typically 30
V/s.
A second switch SW2, which operates in parallel with SW1, is
included in this circuit to reduce pedestal error. Since both
switches will be at the same potential, they will have a differen-
tial effect on the op amp AD711 which will minimize charge
injection effects. Pedestal error is also reduced by the compensa-
tion network RC and CC. This compensation network also reduces
the hold time glitch while optimizing the acquisition time. Using
the illustrated op amps and component values, the pedestal error
has a maximum value of 5 mV over the
±10 V input range. Both
the acquisition and settling times are 850 ns.
+15V
–15V
2200pF
RC
75
CC
1000pF
CH
2200pF
VOUT
ADG431
ADG432
ADG433
SW1
SW2
S
D
+15V
+5V
–15V
AD845
+15V
–15V
VIN
AD711
Figure 2. Fast, Accurate Sample-and-Hold
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADG433BRZ | 制造商:Analog Devices 功能描述:Multiplexer IC |
| ADG433BRZ-REEL | 功能描述:IC SWITCH QUAD SPST 16SOIC RoHS:是 类别:集成电路 (IC) >> 接口 - 模拟开关，多路复用器，多路分解器 系列:LC²MOS 标准包装:1,000 系列:- 功能:多路复用器 电路:1 x 4:1 导通状态电阻:- 电压电源:双电源 电压 - 电源，单路/双路(±):±5V 电流 - 电源:7mA 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-SOIC（0.154"，3.90mm 宽） 供应商设备封装:16-SOIC 包装:带卷 (TR) |
| ADG436 | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual SPDT Switch |
| ADG436_05 | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual SPDT Switch |
| ADG436BN | 功能描述:IC SWITCH DUAL SPDT 16DIP RoHS:否 类别:集成电路 (IC) >> 接口 - 模拟开关，多路复用器，多路分解器 系列:LC²MOS 标准包装:48 系列:- 功能:开关 电路:4 x SPST - NO 导通状态电阻:100 欧姆 电压电源:单/双电源 电压 - 电源，单路/双路(±):2 V ~ 12 V，±2 V ~ 6 V 电流 - 电源:50nA 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-SOIC（0.154"，3.90mm 宽） 供应商设备封装:16-SOIC 包装:管件 |
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