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| 型号： | ADG734BRU |
| 厂商： | Analog Devices Inc |
| 文件页数： | 9/12页 |
| 文件大小： | 0K |
| 描述： | IC SWITCH QUAD SPDT 20TSSOP |
| 产品培训模块： | Switch Fundamentals |
| 标准包装： | 75 |
| 功能： | 开关 |
| 电路： | 4 x SPDT - NC/NO |
| 导通状态电阻： | 4.5 欧姆 |
| 电压电源： | 单/双电源 |
| 电压 - 电源，单路/双路(±)： | 1.8 V ~ 5.5 V，±2.5 V |
| 电流 - 电源： | 1nA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 20-TSSOP |
| 包装： | 管件 |
REV. A
ADG733/ADG734
–6–
Table I. ADG733 Truth Table
A2
A1
A0
EN
ON Switch
XX
X1
None
00
00D1-S1A, D2-S2A, D3-S3A
00
10D1-S1B, D2-S2A, D3-S3A
01
00D1-S1A, D2-S2B, D3-S3A
01
10D1-S1B, D2-S2B, D3-S3A
10
00D1-S1A, D2-S2A, D3-S3B
10
10D1-S1B, D2-S2A, D3-S3B
11
00D1-S1A, D2-S2B, D3-S3B
11
10D1-S1B, D2-S2B, D3-S3B
X = Don’t Care.
Table II. ADG734 Truth Table
Logic
Switch A
Switch B
0
OFF
ON
1ON
OFF
TERMINOLOGY
VDD
Most Positive Power Supply Potential
VSS
Most Negative Power Supply in a Dual Supply Application. In single supply applications, this should be tied to
ground close to the device.
IDD
Positive Supply Current
ISS
Negative Supply Current
GND
Ground (0 V) Reference
S
Source Terminal. May be an input or output.
DDrain Terminal. May be an input or output.
AX
Logic Control Input
EN
Active low device enable
VD (VS)Analog Voltage on Terminals D and S
RON
Ohmic Resistance between D and S
R
ON
On Resistance Match between any Two Channels (i.e., RONmax and RONmin)
RFLAT(ON)
Flatness is defined as the difference between the maximum and minimum value of on resistance as measured over
the specified analog signal range.
IS (OFF)
Source Leakage Current with the Switch “OFF”
ID, IS (ON)
Channel Leakage Current with the Switch “ON”
VINL
Maximum Input Voltage for Logic “0”
VINH
Minimum Input Voltage for Logic “1”
IINL(IINH)
Input Current of the Digital Input
CS (OFF)
“OFF” Switch Source Capacitance. Measured with reference to ground.
CD, CS(ON)
“ON” Switch Capacitance. Measured with reference to ground.
CIN
Digital Input Capacitance
tON
Delay Time Measured between the 50% and 90% Points of the Digital Inputs and the Switch “ON” Condition
tOFF
Delay Time Measured between the 50% and 90% Points of the Digital Input and the Switch “OFF” Condition
tON(EN)Delay Time between the 50% and 90% Points of the EN Digital Input and the Switch “ON” Condition
tOFF(EN)Delay Time between the 50% and 90% Points of the EN Digital Input and the Switch “OFF” Condition
tOPEN
“OFF” Time Measured between the 80% Points of Both Switches when Switching from One Address State to
Another
Charge
A Measure of the Glitch Impulse Transferred Injection from the Digital Input to the Analog Output during Switching
Off Isolation
A Measure of Unwanted Signal Coupling through an “OFF” Switch.
Crosstalk
A Measure of Unwanted Signal that Is Coupled through from One Channel to Another as a Result of Para-
sitic Capacitance
On Response
The Frequency Response of the “ON” Switch
Insertion Loss
The Loss Due to the On Resistance of the switch
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