参数资料
型号: ADG788BCPZ
厂商: Analog Devices Inc
文件页数: 8/11页
文件大小: 0K
描述: IC SWITCH QUAD SPDT 20LFCSP
产品培训模块: iCMOS™ Switches and Multiplexers for Data Acquisition
Switch Fundamentals
标准包装: 1
功能: 开关
电路: 4 x SPDT - NC/NO
导通状态电阻: 4.5 欧姆
电压电源: 单/双电源
电压 - 电源,单路/双路(±): 1.8 V ~ 5.5 V,±2.5 V
电流 - 电源: 1nA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 20-VFQFN 裸露焊盘,CSP
供应商设备封装: 20-LFCSP
包装: 托盘
产品目录页面: 803 (CN2011-ZH PDF)
配用: EVAL-ADG788EBZ-ND - BOARD EVALUATION FOR ADG788
REV.
ADG786/ADG788
–6–
Table I. ADG786 Truth Table
A2
A1
A0
EN
ON Switch
X
1
None
0
D1-S1A, D2-S2A, D3-S3A
0
1
0
D1-S1B, D2-S2A, D3-S3A
0
1
0
D1-S1A, D2-S2B, D3-S3A
0
1
0
D1-S1B, D2-S2B, D3-S3A
1
0
D1-S1A, D2-S2A, D3-S3B
1
0
1
0
D1-S1B, D2-S2A, D3-S3B
1
0
D1-S1A, D2-S2B, D3-S3B
1
0
D1-S1B, D2-S2B, D3-S3B
Table II. ADG788 Truth Table
Logic
Switch A
Switch B
0
OFF
ON
1
ON
OFF
VDD
Most Positive Power Supply Potential
VSS
Most Negative Power Supply in a Dual Supply Application. In single supply applications, this should be tied to
ground close to the device.
IDD
Positive Supply Current
ISS
Negative Supply Current
GND
Ground (0 V) Reference
S
Source Terminal. May be an input or output
D
Drain Terminal. May be an input or output
IN
Logic Control Input
VD (VS)
Analog Voltage on Terminals D, S
RON
Ohmic Resistance between D and S
ΔRON
On Resistance Match between Any Two Channels, i.e., RONmax – RONmin.
RFLAT(ON)
Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured
over the specified analog signal range.
IS (OFF)
Source Leakage Current with the Switch “OFF”
ID, IS (ON)
Channel Leakage Current with the Switch “ON”
VINL
Maximum Input Voltage for Logic “0”
VINH
Minimum Input Voltage for Logic “1”
IINL(IINH)
Input Current of the Digital Input
CS (OFF)
“OFF” Switch Source Capacitance. Measured with reference to ground.
CD, CS(ON)
“ON” Switch Capacitance. Measured with reference to ground.
CIN
Digital Input Capacitance
tON
Delay time measured between the 50% and 90% points of the digital inputs and the switch “ON” condition.
tOFF
Delay time measured between the 50% and 90% points of the digital input and the switch “OFF” condition.
tON(
EN)
Delay time between the 50% and 90% points of the
EN digital input and the switch “ON” condition.
tOFF(
EN)
Delay time between the 50% and 90% points of the
EN digital input and the switch “OFF” condition.
tOPEN
“OFF” time measured between the 80% points of both switches when switching from one address state to another.
Charge
A measure of the glitch impulse transferred Injection from the digital input to the analog output during switching.
Off Isolation
A measure of unwanted signal coupling through an “OFF” switch.
Crosstalk
A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic
capacitance.
On Response
The Frequency Response of the “ON” Switch
Insertion Loss
The Loss Due to the ON Resistance of the Switch.
TERMINOLOGY
B
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