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| 型号： | ADG796ABCPZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 11/24页 |
| 文件大小： | 0K |
| 描述： | IC MUX/DEMUX HEX 2X1 24LFCSP |
| 产品变化通告： | ADG79xx Discontinuance Notice 17/Aug/2010 |
| 标准包装： | 1 |
| 功能： | 多路复用器/多路分解器 |
| 电路： | 6 x 2:1 |
| 导通状态电阻： | 4 欧姆 |
| 电压电源： | 单电源 |
| 电压 - 电源，单路/双路(±)： | 3V，5V |
| 电流 - 电源： | 1nA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 24-LFCSP-VQ（4x4） |
| 包装： | 标准包装 |
| 产品目录页面： | 801 (CN2011-ZH PDF) |
| 其它名称： | ADG796ABCPZ-REELDKR |
ADG796A
Rev. 0 | Page 19 of 24
LDSW BIT
The LDSW bit allows the user to control the way the device
executes the commands loaded during write operations. The
ADG796A executes all commands loaded between two
successive write operations that have set the LDSW bit high.
Setting the LDSW high for every write cycle ensures that the
device executes the command immediately after the LDSW bit
is loaded into the device. This setting can be used when the
desired configuration is achieved by sending a single command
or when the switches are not required to be updated at the same
time. When the desired configuration requires multiple
commands with simultaneous updates, the LDSW bit should be
set low while loading the commands, except for the last one
when the LDSW bit should be set high. Once the last command
with LDSW = high is loaded, the device simultaneously
executes all commands received since the last update.
POWER ON/SOFTWARE RESET
The ADG796A has a software reset function implemented by
the RESETB bit from the second data byte loaded into the device
during a write operation. For normal operation of the multi-
plexers, this bit should be set high. When RESETB = low or after
power-up, the switches from all multiplexers are turned off (open).
READ OPERATION
When reading data back from the ADG796A, the user must
begin with an address byte and R/W bit. Then, the switch
acknowledges that it is prepared to transmit data by pulling
SDA low. Following this acknowledgement, the ADG796A
transmits two bytes on the next clock edges. These bytes contain
the status of the switches, and each byte is followed by an
acknowledge bit. A logic high bit represents a switch in the on
(close) state while a low represents a switch in the off (open)
state. Figure 28 illustrates the entire read sequence.
The bit map accompanying Figure 28 shows the relationship
between the elements of the ADG796A and the bits that
represent their status after a completed read operation.
ADG796 Bit Map
RB15
RB14
RB13
RB12
RB11
RB10
RB9
RB8
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
S1A/D1
S1B/D1
S2A/D2
S2B/D2
S3A/D3
S3B/D3
S4A/D4
S4B/D4
S5A/D5
S5B/D5
S6A/D6
S6B/D6
-
SCL
SDA
A1
A0
RB14
RB15
R/W
RB13 RB12 RB11 RB10 RB9 RB8
RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0
START
CONDITION
BY MASTER
STOP
CONDITION
BY MASTER
ADDRESS BYTE
ACKNOWLEDGE
BY SWITCH
ACKNOWLEDGE
BY SWITCH
ACKNOWLEDGE
BY SWITCH
06
03
6-
01
5
Figure 28. Read Operation
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| ADG796ACCPZ-500RL7 | 制造商:AD 制造商全称:Analog Devices 功能描述:I2C-Compatible, Wide Bandwidth, Hex 2:1 Multiplexer |
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| ADG798HFZ | 功能描述:1 Circuit IC Switch 8:1 10 Ohm 16-CFlatPack 制造商:analog devices inc. 系列:- 包装:管件 零件状态:在售 开关电路:- 多路复用器/解复用器电路:8:1 电路数:1 导通电阻（最大值）:10 欧姆 通道至通道匹配（ΔRon）:1.25 欧姆 电压 -?电源，单（V+）:3 V ~ 5.5 V 电压 - 电源，双（V±）:±2.5V 开关时间（Ton, Tof）（最大值）:30ns，20ns -3db 带宽:55MHz 电荷注入:3pC 沟道电容 （CS(off），CD（off））:13pF，85pF 电流 - 漏泄（IS（off））（最大值）:180nA 串扰:-60dB @ 10MHz 工作温度:-55°C ~ 210°C（TA） 封装/外壳:16-CFlatPack 供应商器件封装:16-CFlatPack 标准包装:1 |
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