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| 型号： | ADL5562ACPZ-R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 11/24页 |
| 文件大小： | 0K |
| 描述： | IC AMP DIFF RF/IF 3.3GHZ 16LFCSP |
| 产品培训模块： | Differential Circuit Design Techniques for Communication Applications |
| 设计资源： | Using ADL5562 Differential Amplifier to Drive Wide Bandwidth ADCs for High IF AC-Coupled Appls (CN0110) |
| 标准包装： | 1 |
| 放大器类型： | RF/IF 差分 |
| 电路数： | 1 |
| 输出类型： | 差分 |
| 转换速率： | 9800 V/µs |
| -3db带宽： | 3.3GHz |
| 电流 - 输入偏压： | 3µA |
| 电流 - 电源： | 80mA |
| 电压 - 电源，单路/双路(±)： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 16-LFCSP-VQ |
| 包装： | 标准包装 |
| 产品目录页面： | 551 (CN2011-ZH PDF) |
| 其它名称： | ADL5562ACPZ-R7DKR |
Data Sheet
ADL5562
Rev. E | Page 19 of 24
SOLDERING INFORMATION
On the underside of the chip scale package, there is an exposed
compressed paddle. This paddle is internally connected to the
ground of the chip. Solder the paddle to the low impedance
ground plane on the PCB to ensure the specified electrical
performance and to provide thermal relief. To further reduce
thermal impedance, it is recommended that the ground planes
on all layers under the paddle be stitched together with vias.
EVALUATION BOARD
Figure 45 shows the schematic of the ADL5562 evaluation board.
The board is powered by a single supply in the 3 V to 3.6 V range.
The power supply is decoupled by 10 F and 0.1 F capacitors.
Table 14 details the various configuration options of the evaluation
board. Figure 46 and Figure 47 show the component and circuit
layouts of the evaluation board.
To realize the minimum gain (6 dB into a 200 Ω load), Input 1
(VIN1 and VIP1) must be used by installing 0 Ω resistors at R3
and R4, leaving R5 and R6 open. R1 and R2 must be 33 Ω for a
50 Ω input impedance.
Likewise, driving Input 2 (VIN2 and VIP2) realizes the middle
gain (12 dB into a 200 Ω load) by installing 0 Ω at R5 and R6
and leaving R3 and R4 open. R1 and R2 must be 29 Ω for a
50 Ω input impedance.
For the maximum gain (15.5 dB into a 200 Ω load), both inputs
are driven by installing 0 Ω resistors at R3, R4, R5, and R6. R1
and R2 must be 40.2 Ω for a 50 input impedance.
The balanced input and output interfaces are converted to
single ended with a pair of baluns (M/A-COM ETC1-1-13).
The balun at the input, T1, provides a 50 single-ended-to-
differential transformation. The output balun, T2, and the
matching components are configured to provide a 200 Ω to 50 Ω
impedance transformation with an insertion loss of about 17 dB.
C3
10F
C4
0.1F
C5
0.1F
C6
0.1F
C7
0.1F
C8
0.1F
C13
0.1F
C11
0.1F
VPOS
08003-
040
R9
34.8
R11
OPEN
J3
R10
34.8
R8
84.5
C10
0.01F
C9
0.01F
P1
T2
J2
AGND
VPOS
GND
R7
84.5
ENBL
ADL5562
9
10
11
12
4
3
2
1
16
15
14
13
5
6
7
8
GND
VCC
VIN1
VIN2
VIP2
VIP1
VON
VOCM
ENBL
VOP
VCC
C12
0.1F
J1
T1
R1
40.2
R2
40.2
R4
0
R3
0
R5
0
R6
0
C1
0.01F
C2
0.01F
Figure 45. Evaluation Board Schematic
Table 14. Evaluation Board Configuration Options
Component
Description
Default Condition
VPOS, GND
Ground and supply vector pins.
VPOS, GND = installed
C3, C4, C5,
C6, C7, C11
Power supply decoupling. The supply decoupling consists of a 10 F capacitor (C3)
to ground. C4 to C7 are bypass capacitors. C11 ac couples VREF to ground.
C3 = 10 F (Size D),
C4, C5, C6, C7, C11 = 0.1 F (Size 0402)
J1, R1, R2, R3,
R4, R5, R6, C1,
C2, C12, T1
Input interface. The SMA labeled J1 is the input. T1 is a 1-to-1 impedance ratio balun
to transform a single-ended input into a balanced differential signal. C1 and C2
provide ac coupling. C12 is a bypass capacitor. R1 and R2 provide a differential 50
input termination. R3 to R6 are used to select the input for the pin-strappable gain.
Maximum gain: R3, R4, R5, R6 = 0 ; and R1, R2 = 40.2 . Middle gain: R5, R6 = 0 ; and R3,
R4 = open; R1, R2 = 33 . Minimum gain: R3, R4 = 0 ; and R5, R6 = open; R1, R2 = 29 .
J1 = installed,
R1, R2 = 40.2 (Size 0402),
R3, R4, R5, R6 = 0 (Size 0402),
C1, C2 = 0.01 F (Size 0402),
C12 = 0.1 F (Size 0402)
T1 = ETC1-1-13 (M/A-COM)
J3, R7, R8, R9,
R10, R11, C9,
C10, C13, T2
Output interface. The SMA labeled J3 is the output. T2 is a 1-to-1 impedance ratio
balun to transform a balanced differential signal to a single-ended signal. C13 is a
bypass capacitor. R7, R8, R9, and R10 are provided for generic placement of matching
components. The evaluation board is configured to provide a 200 to 50 impedance
transformation with an insertion loss of 17 dB. C9 and C10 provide ac coupling.
J3 = installed,
R7, R8 = 84.5 (Size 0402),
R9, R10 = 34.8 (Size 0402),
R11 = open (Size 0402),
C9, C10 = 0.01 F (Size 0402),
C13 = 0.1 F (Size 0402)
T2 = ETC1-1-13 (M/A-COM)
ENBL, P1, C8
Device enable. C8 is a bypass capacitor. When the P1 jumper is set toward the VPOS label,
the ENBL pin is connected to the supply, enabling the device. In the opposite direction,
toward the GND label, the ENBL pin is grounded, putting the device in power-down mode.
ENBL, P1= installed,
C8 = 0.1 F (Size 0402)
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