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| 型号： | ADM1023ARQ |
| 厂商： | ON Semiconductor |
| 文件页数： | 12/16页 |
| 文件大小： | 0K |
| 描述： | IC SENSOR TEMP PREC DUAL 16QSOP |
| 标准包装： | 98 |
| 功能： | 温度监控系统（传感器） |
| 传感器类型： | 内部和外部 |
| 感应温度： | 0°C ~ 120°C，外部传感器 |
| 精确度： | ±1°C 本地，±3°C 远程 |
| 拓扑： | ADC，比较器，多路复用器，寄存器库 |
| 输出类型： | SMBus? |
| 输出警报： | 是 |
| 输出风扇： | 无 |
| 电源电压： | 3 V ~ 5.5 V |
| 工作温度： | 0°C ~ 120°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-QSOP |
| 包装： | 管件 |
ADM1023
Table 12. DEVICE ADDRESSES (Note 1)
ADD0 ADD1 Device Address
line low during the low period before the ninth
clock pulse, known as the Acknowledge bit. All
other devices on the bus remain idle while the
0
0
0
NC
NC
NC
1
1
1
0
NC
1
0
NC
1
0
NC
1
0011 000
0011 001
0011 010
0101 001
0101 010
0101 011
1001 100
1001 101
1001 110
selected device waits for data to be read from or
written to it. If the R/W bit is 0, the master writes
to the slave device. If the R/W bit is 1, the master
reads from the slave device.
2. Data is sent over the serial bus in sequences of
nine clock pulses, 8 bits of data followed by an
Acknowledge bit from the slave device.
Transitions on the data line must occur during the
low period of the clock signal and remain stable
during the high period, because a low-to-high
1. ADD0 and ADD1 are sampled at powerup only.
The serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a
start condition, defined as a high-to-low transition
on the serial data line, SDATA, while the serial
clock line, SCLK, remains high. This indicates
that an address/data stream will follow. All slave
peripherals connected to the serial bus respond to
the start condition and shift in the next 8 bits.
These bits consist of a 7-bit address (MSB first)
plus an R/W bit, which determines the direction of
the data transfer, that is, whether data is written to,
or read from, the slave device.
The peripheral whose address corresponds to the
transmitted address responds by pulling the data
transition when the clock is high may be
interpreted as a stop signal. The number of data
bytes that can be transmitted over the serial bus in
a single read or write operation is limited only by
what the master and slave devices can handle.
3. When all data bytes have been read or written,
stop conditions are established. In write mode, the
master pulls the data line high during the 10th
clock pulse to assert a stop condition. In read
mode, the master device overrides the
Acknowledge bit by pulling the data line high
during the low period before the ninth clock pulse.
This is known as No Acknowledge. The master
then takes the data line low during the low period
before the 10th clock pulse, then high during the
10th clock pulse to assert a stop condition.
1
9
1
9
SCLK
SDATA
0
1
0
1
1
A1
A0
R/W
D7
D6
D5
D4
D3
D2
D1
D0
START BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
ACK. BY
ADM1023
FRAME 2
ADDRESS POINTER REGISTER BYTE
ACK. BY
ADM1023
SCLK (CONTINUED)
1
9
SDATA (CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0
FRAME 3
DATA BYTE
Figure 15. Writing a Register Address to the Address Pointer Register,
then Writing Data to the Selected Register
ACK. BY
ADM1023
STOP BY
MASTER
1
9
1
9
SCLK
SDATA
0
1
0
1
1
A1
A0
R/W
D7
D6
D5
D4
D3
D2
D1
D0
START BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
ACK. BY
ADM1023
FRAME 2
ADDRESS POINTER REGISTER BYTE
ACK. BY
ADM1023
STOP BY
MASTER
Figure 16. Writing to the Address Pointer Register Only
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