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参数资料
| 型号： | ADM1024 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | System Hardware Monitor with Remote Diode Thermal Sensing |
| 中文描述： | 系统硬件监控与远程二极管温度传感器 |
| 文件页数： | 26/28页 |
| 文件大小： | 285K |
| 代理商： | ADM1024 |
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ADM1024
–26–
REV. 0
Table XII. Register 43h,
INT
Interrupt Mask Register 1 (Power-On Default = 00h)
Bit
Name
R/
W
Description
0
1
2
3
4
5
6
7
2.5 V/Ext. Temp2
V
CCP1
V
CC
5 V
Int. Temp
Ext. Temp1
FAN1/AIN1
FAN2/AIN2
Read/
Write
Read/
Write
Read/
Write
Read/
Write
Read/
Write
Read/
Write
Read/
Write
Read/
Write
A one disables the corresponding interrupt status bit for
INT
interrupt.
A one disables the corresponding interrupt status bit for
INT
interrupt.
A one disables the corresponding interrupt status bit for
INT
interrupt.
A one disables the corresponding interrupt status bit for
INT
interrupt.
A one disables the corresponding interrupt status bit for
INT
interrupt.
A one disables the corresponding interrupt status bit for
INT
interrupt.
A one disables the corresponding interrupt status bit for
INT
interrupt.
A one disables the corresponding interrupt status bit for
INT
interrupt.
Table XIII. Register 44h,
INT
Mask Register 2 (Power-On Default = 00h)
Bit
Name
R/
W
Description
0
1
2
3
4
5
6
7
12 V
V
CCP2
Reserved
Reserved
CI
THERM
(Input)
D1 Fault
D2 Fault
Read/
Write
Read/
Write
Read/
Write
Read/
Write
Read/
Write
Read/
Write
Read/
Write
Read/
Write
A one disables the corresponding interrupt status bit for
INT
interrupt.
A one disables the corresponding interrupt status bit for
INT
interrupt.
Power-up default set to Low.
Power-up default set to Low.
A one disables the corresponding interrupt status bit for
INT
interrupt.
A one disables the corresponding interrupt status bit for
INT
interrupt.
A one disables the corresponding interrupt status bit for
INT
interrupt.
A one disables the corresponding interrupt status bit for
INT
interrupt.
Table XIV. Register 46h, Chassis Intrusion Clear (Power-On Default = 00h)
Bit
Name
R/
W
Description
0–6
7
Reserved
Chassis Int. Clear
Read Only
Read/
Write
Undefined, always reads as 00h.
A one outputs a minimum 20 ms active low pulse on the Chassis Intrusion
pin. The register bit clears itself after the pulse has been output.
Table XV. Register 47h, VID0–3/FAN Divisor Register (Power-On Default 0101(VID3–0))
Bit
Name
R/
W
Description
0–3 VID
Read
The VID[3:0] inputs from processor core power supplies to indicate the
operating voltage (e.g., 1.3 V to 3.5 V)
Sets counter prescaler for FAN1 speed measurement
<5:4> = 00 – divide by 1
<5:4> = 01 – divide by 2
<5:4> = 10 – divide by 4
<5:4> = 11 – divide by 8.
Sets counter prescaler for FAN2 speed measurement
<7:6> = 00 – divide by 1
<7:6> = 01 – divide by 2
<7:6> = 10 – divide by 4
<7:6> = 11 – divide by 8.
4–5 FAN1 Divisor
Read/
Write
6–7 FAN2 Divisor
Read/
Write
Table XVI. Register 49h, VID4/Device ID Register (Power-On Default 1000000(VID4))
Bit
Name
R/
W
Description
0
1–7
VID4
Reserved
Read Only
Read Only
VID4 Input from Pentium.
Undefined, always reads as 1000 000(VID4).
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