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参数资料
| 型号： | ADM1026JST-REEL7 |
| 厂商： | ON Semiconductor |
| 文件页数： | 12/55页 |
| 文件大小： | 0K |
| 描述： | IC CNTRL SYS REF/EEPROM 48LQFP |
| 产品变化通告： | MFG CHG Notification ADI to ON Semi Product Obsolescence 30/Sept/2009 |
| 标准包装： | 1 |
| 功能： | 硬件监控器 |
| 传感器类型： | 内部和外部 |
| 感应温度： | 0°C ~ 100°C |
| 精确度： | ±3°C（最小值） |
| 拓扑： | ADC，比较器，多路复用器，寄存器库 |
| 输出类型： | SMBus? |
| 输出警报： | 无 |
| 输出风扇： | 是 |
| 电源电压： | 3 V ~ 5.5 V |
| 工作温度： | 0°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-LQFP（7x7） |
| 包装： | 标准包装 |
| 其它名称： | ADM1026JSTREELDKR |
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ADM1026
2. Data is sent over the serial bus in sequences of nine
clock pulses, 8 bits of data followed by an
acknowledge bit from the slave device. Data
transitions on the data line must occur during the
low period of the clock signal and remain stable
during the high period, because a low-to-high
transition when the clock is high may be interpreted
as a stop signal.
If the operation is a write operation, the first data
byte after the slave address is a command byte.
This tells the slave device what to expect next. It
may be an instruction telling the slave device to
expect a block write, or it may simply be a register
address that tells the slave where subsequent data is
to be written.
Because data can flow in only one direction as
defined by the R/W bit, it is not possible to send a
command to a slave device during a read operation.
Before doing a read operation, it may first be
necessary to do a write operation to tell the slave
what type of read operation to expect and/or the
address from which data is to be read.
3. When all data bytes have been read or written, stop
conditions are established. In write mode, the master
pulls the data line high during the 10th clock pulse
to assert a stop condition. In read mode, the master
device releases the SDA line during the low period
before the ninth clock pulse, but the slave device
does not pull it low (called No Acknowledge). The
master takes the data line low during the low period
before the 10th clock pulse, then high during the
10th clock pulse to assert a stop condition.
*If it is required to perform several read or write operations in
succession, the master can send a repeat start condition instead
of a stop condition to begin a new operation.
1
9
1
9
SCL
SDA
0
1
0
1
1
A1
A0
R/W
D7
D6
D5
D4
D3
D2
D1
D0
START BY
MASTER
FRAME 1
SLAVE ADDRESS
ACK. BY
SLAVE
FRAME 2
COMMAND CODE
ACK. BY
SLAVE
1
9
1
9
SCL
(CONTINUED)
SDA
(CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
FRAME 3
DATA BYTE
ACK. BY
SLAVE
FRAME N
DATA BYTE
ACK. BY
SLAVE
STOP BY
MASTER
Figure 16. General SMBus Write Timing Diagram
1
9
1
9
SCL
SDA
0
1
0
1
1
A1
A0
R/W
D7
D6
D5
D4
D3
D2
D1
D0
START BY
MASTER
FRAME 1
SLAVE ADDRESS
ACK. BY
SLAVE
FRAME 2
DATA BYTE
ACK. BY
MASTER
1
9
1
9
SCL
(CONTINUED)
SDA
(CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
FRAME 3
DATA BYTE
ACK. BY
MASTER
FRAME N
DATA BYTE
NO ACK.
STOP BY
MASTER
Figure 17. General SMBus Read Timing Diagram
http://onsemi.com
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