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参数资料
| 型号： | ADM1026JST |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 电源管理 |
| 英文描述： | Circular Connector; No. of Contacts:28; Series:LJT06R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:19; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:19-28 |
| 中文描述： | 4-CHANNEL POWER SUPPLY SUPPORT CKT, PQFP48 |
| 封装： | 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026BBC, LQFP-48 |
| 文件页数： | 4/56页 |
| 文件大小： | 634K |
| 代理商： | ADM1026JST |
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ADM1026
Parameter
High Level Output Leakage Current, I
OH
Output Low Voltage, V
OL
PWM Output Frequency
DIGITAL OUTPUTS (INT, RESETMAIN, RESETBY)
Output Low Voltage, V
OL
RESET Pulse Width
OPEN DRAIN SERIAL DATABUS OUTPUT (SDA)
Output Low Voltage, V
OL
High Level Output Leakage Current, I
OH
SERIAL BUS DIGITAL INPUTS (SCL, SDA)
Input High Voltage, V
IH
Input Low Voltage, V
IL
Hysteresis
DIGITAL INPUT LOGIC LEVELS (ADD, CI, FAN 0 to 7, GPIO 0 to 16)
7,
8
Input High Voltage, V
IH
Input Low Voltage, V
IL
Hysteresis (Fan 0 to 7)
RESETMAIN, RESETSTBY
RESETMAIN Threshold
RESETSBY Threshold
RESETMAIN Hysteresis
RESETSTBY Hysteresis
DIGITAL INPUT CURRENT
Input High Current, I
IH
Input Low Current, I
IL
Input Capacitance, C
IN
EEPROM RELIABILITY
Endurance
9
Data Retention
10
SERIAL BUS TIMING
Clock Frequency, f
SCLK
Glitch Immunity, t
SW
Bus Free Time, t
BUF
Start Setup Time, t
SU; STA
Start Hold Time, t
HD; STA
SCL Low Time, t
LOW
SCL High Time, t
HIGH
SCL, SDA Rise Time, t
r
SCL, SDA Fall Time, t
f
Data Setup Time, t
SU; DAT
Data Hold Time, t
HD; DAT
Rev. A | Page 4 of 56
Min
140
2.2
2.4
0.8
2.89
3.01
–1
100
10
4.7
4.7
4
4.7
4
250
300
Typ
0.1
75
180
0.1
500
250
2.94
3.05
60
70
20
700
Max
1
0.4
0.4
240
0.4
1
0.8
2.97
3.10
1
400
50
1000
300
Test Conditions/Comments
V
OUT
= V
CC
I
OUT
= 3.0 mA, V
CC
= 3.3 V
I
OUT
= 3.0 mA, V
CC
= 3.3 V
I
OUT
= –3.0 mA, V
CC
= 3.3 V
V
OUT
= V
CC
V
CC
= 3.3 V
V
CC
= 3.3 V
V
CC
= 3.3 V
Falling voltage
Falling voltage
V
IN
= V
CC
V
IN
= 0
See Figure 2 for all parameters.
Unit
μA
V
Hz
V
ms
V
μA
V
V
mV
V
V
mV
V
V
mV
mV
μA
μA
pF
kcycles
Years
kHz
ns
μs
μs
μs
μs
μs
ns
ns
ns
ns
1
All voltages are measured with respect to GND, unless otherwise specified.
2
Typicals are at T
A
= 25°C and represent the most likely parametric norm. Shutdown current typ is measured with V
CC
= 3.3 V.
3
Timing specifications are tested at logic levels of V
IL
= 0.8 V for a falling edge and V
IH
= 2.1 V for a rising edge.
4
Total unadjusted error (TUE) includes offset, gain, and linearity errors of the ADC, multiplexer, and on-chip input attenuators. V
BAT
is accurate only for V
BAT
voltages
greater than 1.5 V (see Figure 15).
5
Total analog monitoring cycle time is nominally 273 ms, made up of 18 ms × 11.38 ms measurements on analog input and internal temperature channels, and
2 ms × 34.13 ms measurements on external temperature channels.
6
The total fan count is based on two pulses per revolution of the fan tachometer output. The total fan monitoring time depends on the number of fans connected and
the fan speed. See the Fan Speed Measurement section for more details.
7
ADD is a three-state input that may be pulled high, low, or left open-circuit.
8
Logic inputs accept input high voltages up to 5 V even when device is operating at supply voltages below 5 V.
9
Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117, and measured at 40°C, +25°C, and +85°C. Typical endurance at +25°C is 700,000 cycles.
10
Retention lifetime equivalent at junction temperature (T
J
) = 55°C as per JEDEC Std. 22 method A117. Retention lifetime based on an activation energy of 0.6 V
derates with junction temperature as shown in Figure 16.
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